EP80579 Datasheet, PDF (1120/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.2.2.2
ICW2[0-1] - Initialization Command Word 2 Register
ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[07:03] is used by the
processor to define the base address in the interrupt vector table for the interrupt
routines associated with each IRQ on the controller. Typical ISA (legacy) ICW2 values
are 08h for the master controller and 70h for the slave controller.
Table 30-7. ICW2[0-1] - Initialization Command Word 2 Register
Description:
View: IA F
Base Address: 0000h (IO)
Offset Start: 021h, 0A1h
Offset End: 021h, 0A1h
Size: 8 bit
Default: XXh
Power Well: Core
Bit Range
07 : 03
02 : 00
Bit Acronym
Bit Description
Sticky
IVBA
IRL
Interrupt Vector Base Address: These bits define the
base address in the interrupt vector table for the interrupt
routines associated with each interrupt request level
input.
Interrupt Request Level: When writing ICW2, these bits
must all be 0. During an interrupt acknowledge cycle,
these bits are programmed by the interrupt controller with
the interrupt to be serviced. This is combined with bits
[07:03] to form the interrupt vector driven onto the data
bus during the second INTA# cycle. The code is a three bit
binary code:
Code
Master Interrupt Slave Interrupt
000
IRQ0
IRQ8
001
IRQ1
IRQ9
010
IRQ2
IRQ10
011I
RQ3
IRQ11
100
IRQ4
IRQ12
101
IRQ5
IRQ13
110
IRQ6
IRQ14
111
IRQ7
IRQ15
Bit Reset
Value
Xh
Xh
Bit Access
WO
WO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1120
August 2009
Order Number: 320066-003US