EP80579 Datasheet, PDF (140/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The EP80579 hardware, where appropriate, supports two general capabilities for error
handling. The first is support for data “poisoning” to propagate errors through the chip.
The second is support for mechanisms to allow software to inspect the cause of the
error.
To allow software to inspect the error, each unit in the EP80579 that is capable of
detecting errors typically provides hardware support to:
• Log sufficient information for software to determine what the error was along with
relevant details on the error.
• Disable error detection and reporting.
• Report if more than one error occurred. At a minimum, the unit will note that a
second error occurred. Optionally, a unit may gather additional information on
subsequent errors such as the type(s) of errors or other relevant details.
A given unit need not support all of these capabilities.To illustrate these capabilities,
consider the EP80579 DRAM interface. DRAM on the EP80579 is protected by ECC, so,
on a read with a double-bit error, the memory controller reports an error. The memory
controller can poison the data return value to inform future consumers of the data that
the data is bad.
For software, registers in the memory controller provide the ability to mask this error
along with logging registers that captures the address that was being read when the
error was encountered. On an unmasked double-bit error, the logging register captures
the address and the memory controller signals the IA-32 core through the FERR/NERR
infrastructure. The error address register is locked at this point, so subsequent errors
will not overwrite it until software handles the error and unlocks the registers by writing
a register to clear the error condition. The memory controller provides a “next error”
register that can capture information on other unmasked errors that occur before
software clears the double-bit error condition.
In general, the CMI will attempt to route requests based on their understanding of the
address space layout of the platform (that is, the amount of installed physical DRAM,
attached PCI Express* devices, etc.). There are several tables throughout the EAS that
define how various parts of the chip handle this routing task:
• Section 10.1, “Overview” and Section 10.2, “IMCH Responses to EDMA
Transactions” describes how the IMCH responses to transactions from the EDMA
engine.
• The memory controller does not perform bounds checking on addresses, error
handling behavior is determined by the upstream agents that pass the request to
the memory controller as Section 5.5.1, “Handling Out-of-Bounds Addresses” on
page 154 describes.
The IA portion uses the standard IA mechanisms to handle cases where this routing
encounters errors (e.g., accessing an unpopulated region of memory). These cases
cause aborts and are escalated through the normal error handling paths. On errors in
requests arriving from the memory target, the IMCH will drop writes (i.e., not forward
them into the IMCH) and poison data returns for reads through the appropriate push/
pull data error signals. These error conditions are reported through IMCH error
reporting registers.
Intel^® EP80579 Integrated Processor Product Line Datasheet
140
August 2009
Order Number: 320066-003US