EP80579 Datasheet, PDF (1664/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.24 Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High
Register (Per Ethernet Channel)
When a Delay_Req message in Master mode, or a Sync message in Slave mode, is
received with no errors, the source UUID and the sequence ID of the message are
captured.
Register
Name
TS_SrcUUIDHi
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SequenceID[15:0]
*Address offsets per channel…
Channel 0 = 0x05C
Channel 1 = 0x07C
Channel 2 = 0x09C
Channel 3 = 0x0BC
Channel 4 = 0x0DC
Channel 5 = 0x0FC
Channel 6 = 0x11C
Channel 7 = 0x13C
SourceUUID_High[47:32]
Table 41-34. Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register
(Per Ethernet Channel)
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
005Ch at
Offset Start: 20h
Offset End: 005Fh at
20h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 : 16
The sequence ID is located in bytes 72 and 73 of the
SequenceID Ethernet message, and is captured in this register in bit
locations [31:16].
15 : 0
SourceUUID_Hi This register contains the upper 16 bits (bits 47:32) of the
gh
source UUID in bit locations [15:0].
Note: This register has no meaning and is not used for the CAN interfaces.
Bit Reset
Value
0000h
0000h
Bit Access
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1664
August 2009
Order Number: 320066-003US