EP80579 Datasheet, PDF (350/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
13.3.2 PCI Bus #0 Configuration Mechanism
The IMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the
configuration cycle is targeting a PCI Bus #0 device.
The Host-NSI Bridge entity within the IMCH is hardwired as Device #0 on PCI Bus #0.
The EDMA Controller within the IMCH is hardwired as Device #1 on PCI Bus #0.
The Host-PEA0 bridge entity within the IMCH is hardwired as Device #2 on PCI Bus #0.
The Host-PEA1 bridge entity within the IMCH is hardwired as Device #3 on PCI Bus #0.
The PCI-to-PCI Bridge entity within the IMCH is hardwired as Device #4 on PCI Bus #0
Configuration cycles to any of the IMCH’s enabled internal devices are confined to the
IMCH and not sent over NSI. Accesses to disabled IMCH internal devices, or devices
#10 to #31 is forwarded over NSI as Type 0 Configuration Cycles. A[1:0] of the NSI
Request Packet for the Type 0 configuration cycle is “00”. Bits 31:2 of the
CONFIG_ADDRESS register is translated to the A[31:2] field of the NSI Request Packet
of the configuration cycle as shown in Figure 13-2. The IICH decodes the Type 0 access
and generates a configuration access to the selected internal device.
Figure 13-2. NSI Type 0 Configuration Address Translation
CONFIG_ADDRESS
31
24 23
16 15
11 10 8 7
210
1
Reserved
0
Device Number Function Register Number x x
NSI Type 0 Configuration Address Extension
31
28 27
24 23
16 15
11 10 8 7
210
Reserved
Device Number Function Register Number 0 0
13.3.3
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and does not lie between the
SECONDARY BUS NUMBER register and the SUBORDINATE BUS NUMBER register for
one of the PCI Express ports, the IMCH will generate a Type 1 NSI Configuration Cycle.
A[1:0] of the NSI request packet for the Type 1 configuration cycle is “01”. Bits 31:2 of
the CONFIG_ADDRESS register is translated to the A[31:2] field of the NSI request
packet of the configuration cycle as shown in Figure 13-3. This NSI configuration cycle
is sent over NSI.
If the cycle is forwarded to the IICH via NSI, the IICH compares the non-zero Bus
Number with the SECONDARY BUS NUMBER and SUBORDINATE BUS NUMBER registers
of its P2P bridges to determine if the configuration cycle is meant for the Primary PCI or
one of the IICH’s PCI Express ports.
Intel^® EP80579 Integrated Processor Product Line Datasheet
350
August 2009
Order Number: 320066-003US