EP80579 Datasheet, PDF (210/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3.9
LPC Interface: Bus 0, Device 31, Function 0
The LPC interface includes the registers listed in Table 7-22 through Table 7-26. These
registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR). See
Chapter 19.0, “LPC Interface: Bus 0, Device 31, Function 0”, Chapter 27.0, “Power
Management”, Chapter 18.0, “System Management”, and Chapter 22.0, “General
Purpose I/O: Bus 0, Device 31, Function 0” for detailed discussion of these registers.
Table 7-22. Bus 0, Device 31, Function 0: Summary of LPC Interface PCI Configuration
Registers
Offset Start Offset End
Register ID - Description
00h
04h
06h
08h
09h
0Dh
0Eh
2Ch
40h
44h
48h
4Ch
60h
61h
62h
63h
64h
68h
69h
6Ah
6Bh
80h
82h
84h
88h
D0h
D4h
D8h
DCh
F0h
F8h
03h
05h
07h
08h
0Bh
0Dh
0Eh
2Fh
43h
47h
48h
4Ch
60h
61h
62h
63h
64h
68h
69h
6Ah
6Bh
81h
83h
85h
88h
D3h
D5h
DBh
DCh
F3h
FBh
“Offset 00h: ID: Vendor Identification Register” on page 734
“Offset 04h: CMD: Device Command Register” on page 735
“Offset 06h: STS: Status Register” on page 736
“Offset 08h: RID: Revision ID Register” on page 737
“Offset 09h: CC: Class Code Register” on page 737
“Offset 0Dh: MLT: Master Latency Timer Register” on page 737
“Offset 0Eh: HTYPE: Header Type Register” on page 738
“Offset 2Ch: SID: Subsystem Identifiers Register” on page 738
“Offset 40h: ABASE: ACPI Base Address Register” on page 739
“Offset 44h: ACTL: ACPI Control Register” on page 739
“Offset 48h: GBA: GPIO Base Address Register” on page 740
“Offset 4Ch: GC: GPIO Control Register” on page 741
“Offset 60h: PARC: PIRQA Routing Control Register” on page 741
“Offset 61h: PBRC: PIRQB Routing Control Register” on page 742
“Offset 62h: PCRC: PIRQC Routing Control Register” on page 742
“Offset 63h: PDRC: PIRQDQ Routing Control Register” on page 743
“Offset 64h: SCNT: Serial IRQ Control Register” on page 744
“Offset 68h: PERC: PIRQEQ Routing Control Register” on page 745
“Offset 69h: PFRC: PIRQF Routing Control Register” on page 745
“Offset 6Ah: PGRC: PIRQG Routing Control Register” on page 746
“Offset 6Bh: PHRC: PIRQH Routing Control Register” on page 747
“Offset 80h: IOD: I/O Decode Ranges Register” on page 747
“Offset 82h: IOE: I/O Enables Register” on page 749
“Offset 84h: LG1: LPC Generic Decode Range 1 Register” on page 750
“Offset 88h: LG2: LPC Generic Decode Range 2 Register” on page 751
“Offset D0h: FS1: FWH ID Select 1 Register” on page 752
“Offset D4h: FS2: FWH ID Select 2 Register” on page 753
“Offset D8h: FDE: FWH Decode Enable Register” on page 754
“Offset DCh: BC: BIOS Control Register” on page 756
“Offset F0h: RCBA: Root Complex Base Address Register” on page 757
“Offset F8h: MANID: Manufacturer ID Register” on page 757
Default
Value
50318086h
0007h
0200h
Variable
060100h
00h
80H
00000000h
00000001h
00h
00000001h
00h
80h
80h
80h
80h
10h
80h
80h
80h
80h
0000h
0000h
0000h
0000h
00112233h
4567h
FFCFh
00h
00000000h
00010F90h
Intel^® EP80579 Integrated Processor Product Line Datasheet
210
August 2009
Order Number: 320066-003US