EP80579 Datasheet, PDF (896/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.1.2
24.2
The Host Controller needs to check for parity errors as a target. If it sees an error, it
must set the detected parity error bit (bit 15 of status). If bit 6 and bit 8 of the
command register are set, it needs to generate SERR#, and set the signalled SERR# bit
in the status register (bit 14).
Slave Interface
The slave interface allows an external master to write or read. The write cycles can be
used to cause certain events or pass messages, and the read cycles can be used to
determine the state of various status bits. The internal Host Controller cannot access
the internal Slave Interface.
SMBus Controller PCI Configuration Register Details
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values and are read-only. Writes to reserved
locations may cause system failure and unpredictable behavior.
Reserved bits are read only.
Table 24-2. Bus 0, Device 31, Function 3: Summary of SMBus Controller PCI Configuration
Registers
Offset Start Offset End
Register ID - Description
00h
02h
04h
06h
08h
09h
0Ah
0Bh
20h
2Ch
2Eh
3Ch
3Dh
40h
F8h
01h
03h
05h
07h
08h
09h
0Ah
0Bh
23h
2Dh
2Fh
3Ch
3Dh
40h
FBh
“Offset 00h: VID: Vendor ID Register” on page 897
“Offset 02h: DID: Device ID Register” on page 897
“Offset 04h: CMD: Command Register” on page 897
“Offset 06h: DS – Device Status Register” on page 898
“Offset 08h: RID: Revision ID Register” on page 899
“Offset 09h: PI: Programming Interface Register” on page 900
“Offset 0Ah: SCC: Sub Class Code Register” on page 900
“Offset 0Bh: BCC: Base Class Code Register” on page 900
“Offset 20h: SM_BASE: SMB Base Address Register” on page 901
“Offset 2Ch: SVID: SVID Register” on page 901
“Offset 2Eh: SID: Subsystem Identification Register” on page 902
“Offset 3Ch: INTLN: Interrupt Line Register” on page 902
“Offset 3Dh: NTPN: Interrupt Pin Register” on page 903
“Offset 40h: HCFG: Host Configuration Register” on page 903
“Offset F8h: MANID: Manufacturer ID Register” on page 904
Default
Value
8086h
5032h
0000h
0280h
Variable
00h
05h
0Ch
00000001h
0000h
0000h
00h
Variable
00h
00010F90h
Intel^® EP80579 Integrated Processor Product Line Datasheet
896
August 2009
Order Number: 320066-003US