EP80579 Datasheet, PDF (865/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-62. Offset 118h: PxCMD[0-1] – Port [0-1] Command Register (Sheet 3 of 3)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 118h, 198h
Offset End: 11Bh, 19Bh
Size: 32 bit
Default: Variable
Power Well: Core
Bit Range
12 : 08
07 : 05
04
03
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Current Command Slot (CCS): Indicates the current
command slot the HBA is processing. This field is valid when
the PxCMD.ST bit is set, and is constantly updated by the
HBA. This field can be updated as soon as the HBA
recognizes an active command slot, or at some point soon
after when it begins processing the command. When
CCS
PxCMD.ST transitions from a ‘1’ to a ‘0’, the HBA will reset
this field to ‘0’. After PxCMD.ST transitions from ‘0’ to ‘1’,
0h
the highest priority slot to issue from next is command slot
0. After the first command has been issued, the highest
priority slot to issue from next is PxCMD.CCS + 1. For
example, after the HBA has issued its first command, if
PxCMD.CCS = 0h and PxCI is set to 3h, the next command
that will be issued is from command slot 1.
Reserved Reserved
0h
FIS Receive Enable (FRE): When set, the HBA may post
received FISes into the FIS receive area pointed to by PxFB
and PxFBU. When cleared, received FISes are not accepted
by the HBA, except for the first D2H register FIS after the
initialization sequence.
FRE
System software must not set this bit until PxFB (PxFBU)
0h
have been programmed with a valid pointer to the FIS
receive area. If software wishes to move the base, this bit
must first be cleared, and software must wait for the
PxCMD.FR bit to be cleared. Software must not clear this bit
while PxCMD.ST is set to ‘1’.
Command List Override (CLO): Setting this bit to '1'
causes PxTFD.STS.BSY and PxTFD.STS.DRQ to be cleared
to '0'. This allows a software reset to be transmitted to the
device regardless of whether the BSY and DRQ bits are still
set in the PxTFD.STS register. The HBA sets this bit to '0'
when PxTFD.STS.BSY and PxTFD.STS.DRQ have been
CLO
cleared to '0'. A write to this register with a value of '0' shall
0h
have no effect.
Bit Access
RO
RO
RW
RW
This bit shall only be set to '1' immediately prior to setting
the PxCMD.ST bit to '1' from a previous value of '0'. Setting
this bit to '1' at any other time is not supported and will
result in indeterminate behavior.
02
POD
Power On Device (POD): The SATA controller does not
support cold presence detect.
Spin-Up Device (SUD): This bit is read/write and defaults
to 0 for HBAs that support staggered spin-up via HCAP.SSS.
This bit is read only ‘1’ for HBAs that do not support
01
SUD
staggered spin-up.
On an edge detect from ‘0’ to ‘1’, the HBA shall start a
COMRESET initialization sequence to the device. Clearing
this bit causes no action on the interface.
Start (ST): When set, the HBA may process the command
list. When cleared, the HBA may not process the command
list. Whenever this bit is changed from a ‘0’ to a ‘1’, the HBA
starts processing the command list at entry ‘0’. Whenever
00
ST
this bit is changed from a ‘1’ to a ‘0’, the PxCI register is
cleared by the HBA upon the HBA putting the controller into
an idle state.
See section 10.2.1 of the AHCI spec for restrictions on when
PxCMD.ST can be set to ‘1’ and cleared to ‘0’.
1h
RO
Variable
RW/RO
0h
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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