EP80579 Datasheet, PDF (543/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.25 Offset 3Dh: INTRPIN - Interrupt Pin Register
Table 16-164.Offset 3Dh: INTRPIN - Interrupt Pin Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 3Dh
Offset End: 3Dh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 3Dh
Offset End: 3Dh
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
Sticky
INTRP
Interrupt Pin: Set to ‘01h’ to indicate PCI Express*
always uses INTA# as its interrupt pin. Once this register is
written, the register value locks and cannot be further
updated.
Bit Reset
Value
01h
Bit Access
RWO
16.4.1.26 Offset 3Eh: BCTRL - Bridge Control Register
This register provides extensions to the PCICMD register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (e.g. PCI
Express*) and some bits that affect the overall behavior of the “virtual” PCI-PCI bridge
embedded within, e.g. VGA compatible address range mapping.
Table 16-165.Offset 3Eh: BCTRL - Bridge Control Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 3Eh
Offset End: 3Eh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 3Eh
Offset End: 3Eh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05 : 04
Bit Acronym
Bit Description
Sticky
Reserved
SRESET
Reserved
Reserved
Secondary Bus Reset:
0 = No hot reset is triggered on the link for the
corresponding PCI Express* port and the PCI
Express* hierarchy domain subordinate to the port.
1 = Setting this bit triggers a hot reset on the link for the
corresponding PCI Express* port and the PCI
Express* hierarchy domain subordinate to the port.
This sends the LTSSM into the Training (or Link)
Control Reset state, which necessarily implies a reset
to the downstream device and all subordinate devices.
Once this bit has been cleared, and the minimum
transmission requirement has been met, the detect state is
entered by both ends of the link. Note also that a
secondary bus reset does not in general reset the primary
side configuration registers of the targeted PCI Express*
port. This is necessary to allow software to specify special
training configuration, such as entry into loopback mode.
Reserved
Bit Reset
Value
0b
0b
0b
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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