EP80579 Datasheet, PDF (556/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.43 Offset 65h: PEANPTR - PCI Express* Next Capabilities Pointer Register
This register identifies the next PCI Express* capability structure.
Table 16-182.Offset 65h: PEANPTR - PCI Express Next Capabilities Pointer Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 65h
Offset End: 65h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 65h
Offset End: 65h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 00
Bit Acronym
Bit Description
PEA_NCP
Next Capability Pointer: This field contains that value
00b to indicate that there are no additional capability
structures.
Sticky
Bit Reset
Value
00h
Bit Access
RO
16.4.1.44 Offset 66h: PEACAPA - PCI Express* Features Capabilities Register
This register identifies PCI Express* device type and associated capabilities.
Table 16-183.Offset 66h: PEACAPA - PCI Express Features Capabilities Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 66h
Offset End: 67h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 66h
Offset End: 67h
Size: 16 bit
Default: 0041h
Power Well: Core
Bit Range
15 : 14
13 : 09
08
07 : 04
03 : 00
Bit Acronym
Bit Description
Sticky
Reserved
CIMN
SIMP
DPT
CAPV
Reserved
Capability Interrupt Message Number: If the function
is allocated more than one MSI interrupt number, this field
contains the offset between the base Message Data and
the MSI Message that is generated when any of the status
bits in either the Slot Status or Root Port Status registers
of this capability structure are set. Hardware updates this
field so that it is correct if the number of MSI Messages
assigned to the device (based on the setting of the Multiple
Message Enable bits in the MSI Capabilities register).
Slot Implemented: BIOS must set this bit at boot time if
the PCI Express* link associated with this port is connected
to a slot (as compared to being connected to a
motherboard component, or being disabled).
0 = Slot not implemented.
1 = Slot implemented.
Device/Port Type: Hardwired to a value of “4” hex to
indicate a root port.
Capability Version: Hardwired to 1h to indicate
compliance with the PCI Express* Interface Specification,
Rev 1.0a.
Bit Reset
Value
00b
00000b
0b
4h
1h
Bit Access
RO
RWO
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
556
August 2009
Order Number: 320066-003US