EP80579 Datasheet, PDF (1399/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• Disable packet transmission or schedule the disabling of transmission after the
current packet completes.
Resumption of transmission may occur after:
• Expiration of the PAUSE timer
• Reception of on XON frame (a frame with its PAUSE timer set to 0)
Either condition clears the Device Status Register (STATUS.TXOFF) and transmission
may resume. Hardware records the number of received XON frames.
37.5.8.5.2 “Discard PAUSE Frames” & “Pass MAC Control Frames”
Two bits in the Receive Control Register are implemented specifically for control over
receipt of PAUSE and MAC control frames. These bits are Discard PAUSE Frames
(RCTL.DPF) and Pass MAC Control Frames (RCTL.PMCF). See “RCTL – Receive Control
Register” on page 1474 for explicit definitions.
RCTL.DPF bit will force the discarding of any valid PAUSE frame addressed to the
device's station address. If the packet is a valid PAUSE frame and is addressed to the
station address (receive address [0]), the device will not pass the packet to host
memory if RCTL.DPF bit is set to logic high. However, if a flow control packet is sent to
the station address, and is a valid flow control frame, it will be DMA'd when RCTL.DPF is
set to zero. This bit has no affect on PAUSE operation, only the DMA function.
RCTL.PMCF bit allows for the passing of any valid MAC control frames to the system
which do not have a valid PAUSE opcode. In other words, the frame must have the
correct MAC control frame multicast address (or the MAC station address) as well as
the correct type field match with the FCT register, but will not have the defined PAUSE
opcode of 0x0001. Frames of this type are DMA'd to host memory when RCTL.PMCF is
logic high.
37.5.8.5.3 Transmission of PAUSE Frames
Transmission of PAUSE frames is enabled by software with the Device Control Register
(CTRL.TFCE).
Note:
Similar to the reception flow control packets mentioned above, XOFF packets may be
transmitted only if this configuration has been negotiated between the link partners via
the Auto-Negotiation process. In other words, the setting of this bit indicates the
desired configuration. The resolution of the Auto-Negotiation process is indicated in
“Physical Layer Auto-Negotiation & Link Setup Features” on page 1394.
The content of the Flow Control Receive Threshold High Register determines at what
point hardware transmits a PAUSE frame. Hardware monitors the fullness of the receive
FIFO and compares it with the contents of FCRTH. When the threshold is reached,
hardware sends a PAUSE frame with its pause time field equal to FCTTV register. Once
the receive buffer fullness reaches the low water mark, hardware sends an XON
message (a PAUSE frame with a timer value of 0). Software enables this capability with
the Flow Control Receive Threshold Low Register (FCRTL.XONE).
Hardware will send one more PAUSE frame if it has previously sent one and the FIFO
overflows (so the threshold must not be set greater than the FIFO size). This is
intended to minimize the amount of packets dropped if the first PAUSE frame does not
reach its target. Since the secure receive packets use the same data path, the behavior
is identical when secure packets are received.
Note:
The transmission of Flow Control frames should only be enabled in full duplex mode per
the IEEE 802.3 standard. Software should ensure that the transmission of flow control
packets is disabled when the device is operating in half-duplex mode.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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