EP80579 Datasheet, PDF (1757/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 48-19. Power Management Interface Signals (Sheet 2 of 2)
Signal Name
PWRBTN#
RI#
SYS_RESET#
RSMRST#
SUS_STAT#
IO Type
Direction
Ball
Count
LVTTL,3.3V I
1
LVTTL,3.3V I
1
LVTTL,3.3V I
1
LVTTL,3.3V I
1
LVTTL,3.3V O
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
BSC
Power Button: Causes SMI or SCI to indicate to
system request to go to a sleep state. If already
in sleep state, will cause a wake event. If
PWRBTN# is pressed for four seconds, will cause
unconditional transition (power button override)
to the S5 state. Override will occur even if the
system is in the S3 or S4 state.
This signal has an internal pullup resistor and
has an internal 16 ms de-bounce on the input.
BSC/
XOR
output
Ring Indicate: From the modem interface. Can
be enabled as a wake event and is preserved
during power failures.
BSC
System Reset: This pin forces an internal reset
after being debounced. The EP80579 will reset
immediately if the SMBus is idle; otherwise, it
will wait up to 25 ms ± 2 ms for the SMBus to
idle before forcing a reset on the system.
Resume Well Reset: Used for resetting the
resume well. An external RC circuit is required
to guarantee that the resume well power is valid
prior to RSMRST# going high.
BSC
Suspend Status: This signal is asserted to
indicate that the system will be entering a low
power state soon. This can be monitored by
devices with memory that need to switch from
normal refresh to suspend refresh mode. It can
also be used by other peripherals as an
indication that they must isolate their outputs
that may be going to powered-off planes.
This signal is called LPCPD# on the LPC I/F.
SUSCLK
LVTTL,3.3V O
1
VRMPWRGD
LVTTL,3.3V I
1
TOTAL
14
BSC
BSC
Suspend Clock: Output of the RTC clock
generator circuit (32.768 kHz). SUSCLK will
have a duty cycle that can be as low as 30% or
as high as 70%.
Voltage Regulator Power Good: This is the
processor’s VRM Power Good, and will save an
external AND gate. This signal is internally
ANDed with the ATX power supply’s PWROK
signal. Traditionally, this AND gate has been
external to the chipset.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1757