EP80579 Datasheet, PDF (593/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-215.Offset 150h: COREDMASK - Correctable Error Detect Mask Register (Sheet 2
of 2)
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 150h
Offset End: 153h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 150h
Offset End: 153h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
06
05 : 01
00
Bit Acronym
Bit Description
Sticky
Bad TLP Error Detect MaskOPTIONAL. This bit is sticky
through system reset.
BTEDM
0 = Detect Bad TLP error.
Y
1 = Disable Bad TLP error detection.
Reserved Reserved
REDM
Receiver Error Detect MaskOPTIONAL. This bit is sticky
through system reset.
0 = Detect Receiver error.
Y
1 = Disable Receiver Error error detection.
Bit Reset
Value
0b
0000b
0b
Bit Access
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
593