EP80579 Datasheet, PDF (493/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.47 Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register
Captures the address of the first uncorrectable error encountered by the scrub engine
for a periodic memory scrub. The value in this register is only valid if the Uncorrectable
Scrubber Data Error bit in the DRAM_FERR register or DRAM_NERR register has been
set. The bits in this register are sticky through reset.
Table 16-101.Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: A8h
Offset End: ABh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31
30 :02
01 :00
Bit Acronym
Bit Description
Sticky
Reserved Reserved
SEADD
Scrub Error Address: This field is updated when an
uncorrectable error is encountered by the periodic memory
scrubber and that scrub error causes the DRAM.FERR field
to be updated, i.e. if the uncorrectable scrub error is the
first error after the DRAM_FERR register is cleared. This
Y
field is set by hardware and represents a physical address.
The mapping is DRAM_SCRB_ADD[30:02] = system
address[34:6]. This field is only reset to zero by a PWRGR
reset.
Reserved Reserved
Bit Reset
Value
0b
0000000h
00b
Bit Access
RO
RO
RO
16.2.1.48 Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error Counter Register
Counter for SEC errors occurring for rank 0 in the memory system. The rank counters
for SEC and DED errors are implemented using a leaky bucket algorithm (see Section
11.4.7, “DDR2 MR and EMR settings”). The error count returned when this register is
read is not an absolute count over time, but the sum of errors during a current
specified time period plus half of the accumulated errors from past time periods. When
a time period expires (determined by the Spare Control register, (see Section
16.1.1.48, “Offset 90h: SPARECTL - SPARE Control Register”), the sum of the current
time period accumulated errors and a value equal to half of the past accumulated
errors is retained. Half of this registered error value will be added to the errors
accumulated during the next time period. This method is employed, because it is not
the absolute number of errors that is most interesting, but the rate that errors occur.
When this register is written, the counter holding the number of errors with the current
time period is updated. Because of this described structure, reading back the register
will only return the same value written if no time period has expired between the write
and the read. A write to this register does clears out any error residue that may exist
from past time periods. The EP80579 tracks SEC and DED events on a per-rank basis
within the DIMMs installed in the system.
The bits in this register are sticky through reset.
Note:
Writing this register with a value above threshold will trigger an error.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
493