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Table 5-25. Summary of Memory Controller Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The DRAM_EMASK, DRAM_SCICMD, DRAM_SMICMD, DRAM_SERRCMD, and
DRAM_MCERRCMD registers enable and mask error reporting.
Logging Details
Memory Controller captures additional error logging information in the following registers:
• Uncorrectable read errors: DRAM_DED_ADD.
• Uncorrectable scrubber data errors: DRAM_SCRB_ADD.
• Correctable read errors: DRAM_SECF_ADD, DRAM_SECF_SYNDROME,
DRAM_SECN_ADD, DRAM_SECN_SYNDROME.
• Error threshold detect: RANKTHREX, THRESH_SEC0, THRESH_SEC1, THRESH_DED,
DRAM_SEC_R0, DRAM_SEC_R1, DRAM_DED_R0, DRAM_DED_R1.
Additional logging information is not captured for the remaining errors in Table 5-24.
With the exception of DRAM_SECN_ADD and DRAM_SECN_SYNDROME, all of the logging
information that the memory controller captures relates to the “first” error.
Reporting Multiple The DRAM_NERR register captures the “next” errors seen by the memory controller. This
Errors
register indicates up to one additional error (beyond the first error) of each type.
Data Poisoning
Memory Controller passes along error information to poison data both on inbound (from
memory) data and outbound (to memory) data.
For additional details on error handling in the memory controller, see Section 11.5,
“Error Handling”.
5.6
5.6.1
Error Reporting by AIOC Devices
The AIOC devices continue to use the native error reporting infrastructure that each
unit provides. Primarily, this infrastructure relies on one or more side-band error
signals from each AIOC device that can signal an error along with parity protection on
key interfaces. The AIOC native error reporting mechanisms are then bridged into the
PCI framework that the EP80579 uses to expose AIOC devices to IA. Although AIOC
devices present a PCI interface to IA, they do not implement PCI error reporting
capabilities such as SERR. As a result, the native signals from the AIOC devices are
bridged onto PCI INTx or MSI signals. This implies that the driver software provides all
error handling for AIOC units¹.
The following sections describe the error reporting for each of the AIOC units along with
transaction responses. The per-unit presentations are organized by the PCI device in
which the units materialize.
Gigabit Ethernet MAC
The Gigabit Ethernet MAC units each signal error conditions through three interrupt
signals: Functional 0, Functional 1, and Error. Software uses the IMS0, IMS1, and IMS2
configuration registers in a Gigabit Ethernet MAC to map error conditions onto the
Functional 0, Functional 1, and Error interrupt signals, respectively. Depending on the
configuration, error and functional events may share an interrupt (e.g., software may
configure the functional 1 interrupt to signal both error and functional events);
typically, software will configure a MAC to deliver its error events separately through
only the error interrupt.
Table 5-26 summarizes the error conditions that the Gigabit Ethernet MAC captures.
1. If PCI abstractions such as SERR were used, this would not be the case. Platform and/or O/S software would also be involved
in error handling for the devices even if the involvement is limited to generating a blue screen.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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