EP80579 Datasheet, PDF (198/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers
Mapped Through EDMALBAR Memory BAR (Sheet 2 of 3)
Offset Start Offset End
Register ID - Description
Default
Value
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
68h
6Ch
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
C0h
C4h
0Bh
0Fh
13h
17h
1Bh
1Fh
23h
27h
2Bh
2Fh
43h
47h
4Bh
4Fh
53h
57h
5Bh
5Fh
63h
67h
6Bh
6Fh
83h
87h
8Bh
8Fh
93h
97h
9Bh
9Fh
A3h
A7h
ABh
AFh
C3h
C7h
“Offset 08h: CDAR0 - Channel 0 Current Descriptor Address Register” on page 657 00000000h
“Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register” on
page 658
00000000h
“Offset 10h: SAR0 - Channel 0 Source Address Register” on page 658
00000000h
“Offset 14h: SUAR0 - Channel 0 Source Upper Address Register” on page 659
00000000h
“Offset 18h: DAR0 - Channel 0 Destination Address Register” on page 659
00000000h
“Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address Register” on page 660 00000000h
“Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register” on page 661 00000000h
“Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper Address Register” on
page 662
00000000h
“Offset 28h: TCR0 - Channel 0 Transfer Count Register” on page 662
00000000h
“Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register” on page 663
00000000h
“Offset 40h: CCR1 - Channel 1 Channel Control Register” on page 665
00000000h
“Offset 44h: CSR1 - Channel 1 Channel Status Register” on page 665
00000000h
“Offset 48h: CDAR1 - Channel 1 Current Descriptor Address Register” on page 665 00000000h
“Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register” on
page 666
00000000h
“Offset 50h: SAR1 - Channel 1 Source Address Register” on page 666
00000000h
“Offset 54h: SUAR1 - Channel 1 Source Upper Address Register” on page 666
00000000h
“Offset 58h: DAR1 - Channel 1 Destination Address Register” on page 667
00000000h
“Offset 5Ch: DUAR1 - Channel 1 Destination Upper Address Register” on page 667 00000000h
“Offset 60h: NDAR1 - Channel 1 Next Descriptor Address Register” on page 667 00000000h
“Offset 64h: NDUAR1 - Channel 1 Next Descriptor Upper Address Register” on
page 668
00000000h
“Offset 68h: TCR1 - Channel 1 Transfer Count Register” on page 668
00000000h
“Offset 6Ch: DCR1 - Channel 1 Descriptor Control Register” on page 668
00000000h
“Offset 80h: CCR2 - Channel 2 Channel Control Register” on page 669
00000000h
“Offset 84h: CSR2 - Channel 2 Channel Status Register” on page 669
00000000h
“Offset 88h: CDAR2: Channel 2 Current Descriptor Address Register” on page 669 00000000h
“Offset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Register” on
page 670
00000000h
“Offset 90h: SAR2 - Channel 2 Source Address Register” on page 670
00000000h
“Offset 94h: SUAR2 - Channel 2 Source Upper Address Register” on page 670
00000000h
“Offset 98h: DAR2 - Channel 2 Destination Address Register” on page 671
00000000h
“Offset 9Ch: DUAR2 - Channel 2 Destination Upper Address Register” on page 671 00000000h
“Offset A0h: NDAR2 - Channel 2 Next Descriptor Address Register” on page 671 00000000h
“Offset A4h: NDUAR2 - Channel 2 Next Descriptor Upper Address Register” on
page 672
00000000h
“Offset A8h: DCR2 - Channel 2Transfer Control Register” on page 672
00000000h
“Offset ACh: DCR2 - Channel 2 Descriptor Control Register” on page 672
00000000h
“Offset C0h: CCR3 - Channel 3 Channel Control Register” on page 673
00000000h
“Offset C4h: CSR3 - Channel 3 Channel Status Register” on page 673
00000000h
Intel^® EP80579 Integrated Processor Product Line Datasheet
198
August 2009
Order Number: 320066-003US