EP80579 Datasheet, PDF (1200/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 33-35. Offset 10h: WDTCR - WDT Configuration Register (Sheet 2 of 2)
Description:
View: IA F
Base Address: Base (IO)
Offset Start: 10h
Offset End: 10h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
04 : 03
02
01 : 00
Reserved Reserved
WDT Prescaler Select: The WDT provides two options
for prescaling the main Down Counter. The preload values
are loaded into the main down counter right justified. The
prescaler adjusts the starting point of the 35-bit down
counter.
0 = The 20-bit Preload Value is loaded into bits 34:15 of
WDT_PRE_SEL
the main down counter. The resulting timer clock is
the PCI Clock (33 MHz) divided by 2¹⁵. The
approximate clock generated is 1 KHz, (1 ms to 10
min). (Default)
1 = The 20-bit Preload Value is loaded into bits 24:05 of
the main down counter. The resulting timer clock is
the PCI Clock (33 MHz) divided by 2⁵. The
approximate clock generated is 1 MHz, (1 µs to 1sec)
WDT_INT_TYPE: The WDT timer supports
programmable routing of interrupts. The set of bits allows
the user to choose the type of interrupt desired if the WDT
reached the end of the first stage without being reset. The
interrupt status is reported in the WDT General Interrupt
WDT_INT_TYPE ^{Status register.}
00 SERIRQ (Default)
01 NMI
10 SMI
11 Disabled
Note: SERIRQ is Active Low
Bit Reset
Value
00h
0h
00h
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1200
August 2009
Order Number: 320066-003US