EP80579 Datasheet, PDF (334/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.9.2.2
12.9.2.3
12.9.2.4
The following bits are defined in the CCR:
• Start: initiate a new transfer (requires that the CSR be appropriately cleared)
• Stop: abort the current transfer (immediately)
• Suspend: suspend the current transfer (upon completion of the current descriptor)
• Channel Resume: resume a suspended transfer (retrieve the descriptor indicated
by NDAR/NDUAR from local memory, and proceed with execution per the value
returned). Requires that the stopped and abort status bits in the CSR be clear to
take effect and will automatically clear end of chain and end of transfer flags.
Refer to “Offset 00h: CCR0 - Channel 0 Channel Control Register” on page 653 for the
format of the CCR.
Channel Status Register – CSR
Channel Status Register (CSR) contains flags to indicate the channel status. The
register is read by application software to get the current channel status and to
determine the source of interrupts. CSR is cleared to zero on power-on or system reset.
This is a read/write register.
The following bits are defined in CSR:
• Channel Active: transfer in progress
• Aborted: transfer encountered an error
• Stopped: transfer stopped via software request (Stop bit detected)
• Suspended: transfer suspended via software request (Suspend bit detected)
• End of Transfer: channel has completed execution of (at least one) descriptor
• End of Chain: channel has completed execution of the terminal descriptor (null
NDAR/NDUAR)
Refer to “Offset 04h: CSR0 - Channel 0 Channel Status Register” on page 656 for the
format of CSR.
Current Descriptor Address Register – CDAR
The Current Descriptor Address Register (CDAR) contains the lower 32-bits of the
address for the current chain descriptor in local system memory. The CDAR is cleared
to zero on power-on or system reset, and is loaded automatically with the value from
the Next Descriptor Address Register (NDAR) when a new block transfer is initiated.
This register is read-only, and may be polled by software to monitor the progress of the
channel as it traverses the descriptor chain.¹
Current Descriptor Upper Address Register – CDUAR
The upper address will not be used in the EP80579, which is limited to 32-bit
addressing.
The Current Descriptor Upper Address Register (CDUAR) contains the upper 32-bits of
the address of the current chain descriptor in local system memory. The CDUAR is
cleared to zero on power-on or system reset and is loaded automatically with the value
from the Next Descriptor Upper Address Register (NDUAR) when a new block transfer is
initiated. This register is read-only.¹
1. Note that the IMCH does not provide an interlock to guarantee that consecutive reads to the CDAR/CDUAR pair return
portions of the same descriptor in the event of a collision between the read accesses and a descriptor load operation. If
software requires knowledge of the current descriptor, the “Suspend” function must be invoked prior to polling these
registers.
Intel^® EP80579 Integrated Processor Product Line Datasheet
334
August 2009
Order Number: 320066-003US