EP80579 Datasheet, PDF (415/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-32. Offset C4h: TOLM - Top of Low Memory Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: C4h
Offset End: C5h
Size: 16 bit
Default: 0800h
Power Well: Core
Bit Range
15 : 11
10 : 00
Bit Acronym
Bit Description
Sticky
TOLM
Reserved
Top of Low Memory: This register corresponds to bits 31
to 27 of the system address which is 1 greater than the
maximum DRAM location below 4 Gbyte. Configuration
software must set this value to either the maximum
amount of memory in the system or to the minimum
address allocated for PCI memory or the graphics aperture,
whichever is smaller. Address bits 26:00 are assumed to be
0 for the purposes of address comparison. Addresses equal
to or greater than the TOLM, and less than 4 G, are treated
as non-memory accesses. All accesses less than the TOLM
are treated as DRAM accesses (except for the 15–16 Mbyte
or PAM gaps).
This register must be set to at least 0800h, for a minimum
of 128 Mbyte of DRAM. There is also a minimum of 128
Mbyte of PCI space, since this register is on a 128 Mbyte
boundary.
Configuration software must set this value to either the
maximum amount of memory in the system (same as
DRB3), or to the lower 128 Mbyte boundary of the Memory
Mapped IO range, whichever is smaller.
Programming example:
1100_0b = 3 Gbyte (assuming that DBR7 is set > 4
Gbyte):
An access to 0_C000_0000h or above (but <4 Gbyte) is
considered above the TOLM and therefore not to DRAM. It
may go to one of the PEA ports or NSI or be subtracted and
decoded to NSI. An access to 0_BFFF_FFFFh and below is
considered below the TOLM and go to DRAM.
Reserved
Bit Reset
Value
00001b
000h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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