EP80579 Datasheet, PDF (830/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-20. Offset 40h: PTIM – Primary Timing Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 40h
Offset End: 41h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
PPE0
IE0
TIMO
Device 0 Prefetch/Posting Enable (PPE0): When this
bit is set, prefetch and posting to the IDE data port is
enabled for this drive.
Device 0 IORDY Sample Point Enable (IE0): When
this bit is set, IORDY sampling will be enabled for this
drive. When this bit is cleared, IORDY sampling is disabled
for this drive.
Device 0 Fast Timing Bank (TIM0): When cleared,
accesses to the data port will use compatible timings for
this drive. When set, accesses to the data port will use bits
13:12 for the IORDY sample point, and bits 9:8 for the
recovery time
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
23.1.2.2
23.1.2.3
STIM – Secondary Timing Register
See the above register description for Primary IDE Timing.
Offset 44h: D1TIM – Device 1 IDE Timing Register
The values in this register are only valid if the “Separate Timing Enable” bit is set in the
timing registers. Bits 7:4 are used by device 1 on secondary if bit 14 of offset 42h is
set, and bits 3:0 are used by device 1 on primary if bit 14 of offset 40h is set.
Table 23-21. Offset 44h: D1TIM – Device 1 IDE Timing Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: 44h
Offset End: 44h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 06
Bit Acronym
Bit Description
Sticky
SISP1
Secondary Device 1 IORDY Sample Point (SISP1):
Determines the number of 33 MHz clocks between IDE
IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Bit Reset
Value
00h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
830
August 2009
Order Number: 320066-003US