EP80579 Datasheet, PDF (1900/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
49.5.17.3 SSP AC Characteristics
Table 49-97. SSP Timing Values and Test Conditions
Symbol
Parameter
Min
Nominal
Max
Units Notes
Clock period of SSP_SCLK when the
SSP_SCLK clock is being generated from the
-
271
-
ns 1, 3, 4
internally generated 3.6864 MHz clock
SSP_SCLK clock period that can be
-
produced when the clock is being
generated from the external
542
-
3.6864 MHz clock via SSP_EXTCLK
-
ns
1, 3
Clock period when the clock is being
SSP_EXTCLK
generated from the externally supplied
maximum clock rate of 3.6864 MHz
271
-
clock
-
ns
1, 3
T₁
Output Valid Delay from SSP_EXTCLK
to SSP_SCLK in external clock mode
2
-
15
ns
1, 3
Input Setup time for data prior to the
T₂
valid edge of SSP_SCLK. These signals
15
-
include SSP_RXD.
-
ns
1, 5
Input hold time for data after the valid
T₃
edge of SSP_SCLK. These signals
include SSP_SRXD.
0
-
-
ns 1, 3, 5
SSP_SCLK clock to output valid delay
T₄
from output signals. These signals
-
include SSP_TXD and SSP_SFRM.
-
6
ns
1, 2,
3, 5
Output data hold valid from valid edge
T₅
of SSP_SCLK. These signals include
1
SSP_TXD and SSP_SFRM.
-
-
ns
1, 2,
3, 5
Notes:
1.
Timing was designed for a system load between 5pF and 40pF
2.
Clock jitter on the SSP_SCLK is designed to be an average of the specified clock frequency. The
SSPSCLK jitter specification is unspecified.
3.
Guaranteed by design. These values are typical values seen for this process, but not measured
during production testing.
4.
For low-power SKU configured for internal mode the SSP_SCLK is 360 ns from an internal generated
2.777 MHz clock.
5.
For reference purposes, the timing diagram shows a positive clock edge launch and a positive clock
edge capture, however, depending on the frame format selected, each transmitted bit is driven on
either the rising or falling edge of SSP_SCLK, and is sampled on the opposite clock edge.
Figure 49-46.SSP Interface Timing Diagram
SSP_EXTCLK
SSP_SCLK
SSP_RXD
SSP_TXD
SSP_SFRM
T1
T2
T3
T₄
T5
B6590-02
Intel^® EP80579 Integrated Processor Product Line Datasheet
1900
August 2009
Order Number: 320066-003US