EP80579 Datasheet, PDF (407/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.23 Offset 5Fh: PAM6 - Programmable Attribute Map 6 Register
This register controls the read, write, and shadowing attributes of the BIOS areas from
0E8000h-0EFFFFh.
Table 16-25. Offset 5FH: PAM6 - Programmable Attribute Map 6 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 5Fh
Offset End: 5Fh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 : 06
05 : 04
03 : 02
01 : 00
Bit Acronym
Bit Description
Sticky
Reserved
HIENABLE
Reserved
LOENABLE
Reserved
Attribute Register 0EC000-0EFFFF: This field controls
the steering of read and write cycles that address the BIOS
area from 0EC000 to 0EFFFF.
Encoding Description
00
DRAM Disabled - All accesses are directed to
NSI
01
Read-Only - All reads are serviced by DRAM.
All writes are forwarded to NSI
10
Write Only - All writes are sent to DRAM.
Reads are serviced by NSI
11
Normal DRAM Operation - All reads and
writes are serviced by DRAM
Reserved
Attribute Register 0E8000-0EBFFF: This field controls
the steering of read and write cycles that address the BIOS
area from 0E8000 to 0EBFFF.
Encoding Description
00
DRAM Disabled - All accesses are directed to
NSI
01
Read-Only - All reads are serviced by DRAM.
All writes are forwarded to NSI
10
Write Only - All writes are sent to DRAM.
Reads are serviced by NSI
11
Normal DRAM Operation - All reads and
writes are serviced by DRAM
Bit Reset
Value
00b
00b
00b
00b
Bit Access
RW
RW
16.1.1.24 Offset 9Ch: DEVPRES - Device Present Register
The Device Present bits can be used to enable/disable devices within the IMCH and
make their PCI configuration space respectively visible/invisible to software. The Device
Present bits convey when cleared that the corresponding device is never available.
When a bit is 0, the configuration space associated with that device is hidden, returning
all 1’s for all configuration register reads just as if the cycle terminated with a master
abort on PCI. For the two PCIe* devices listed the I/O buffers and compensation
associated with those devices are disabled and tri-stated. When a bit is 1, the
configuration space associated with that device is accessible. For the two PCIe* devices
the I/O buffers and compensation are enabled.
Note:
BIOS should write this register as part of its power on configuration sequence.
Bits within this register are broken into two categories “RWO or RO” and “RW” and are
functionally defined below.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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