EP80579 Datasheet, PDF (66/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
16-342 Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper Address Register ............... 676
16-343 Offset E8h: TCR3 - Channel 3 Transfer Count Register .......................................... 676
16-344 Offset ECh: DCR3 - Channel 3 Descriptor Control Register .................................... 677
16-345 Offset 100h: DCGC - EDMA Controller Global Command ....................................... 677
16-346 Offset 104h: DCGS - EDMA Controller Global Status ............................................ 678
16-347 Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers Mapped Through
NSIBAR Memory BAR ........................................................................................ 679
16-348 Offset 00h: SNSIVCECH - NSI Virtual Channel Enhanced Capability Header Register . 680
16-349 Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1 ................................ 680
16-350 Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2 ...................................... 681
16-351 Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register ........................................ 682
16-352 Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register .......................... 682
16-353 Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register .............................. 683
16-354 Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register .............................. 684
16-355 Offset 80h: NSIRCILCECH - NSI Root Complex Internal Link Control Enhanced Capability
Header Register .............................................................................................. 684
16-356 Offset 84h: NSILCAP - NSI Link Capabilities Register ........................................... 685
17-1 Bus 0, Device 31, Function 0: Summary of Root Complex Configuration Registers Mapped
Through RCBA Memory BAR ............................................................................... 689
17-2 RCBA Base Address Registers in the IA F View ...................................................... 690
17-3 Offset 0000h: VCH - Virtual Channel Capability Header Register ............................. 691
17-4 Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register .................................. 691
17-5 Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register .................................. 692
17-6 Offset 000Ch: PVC - Port Virtual Channel Control Register ..................................... 692
17-7 Offset 000Eh: PVS -Port Virtual Channel Status Register ........................................ 693
17-8 Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability Register ..................... 693
17-9 Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register ......................... 694
17-10 Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register.......................... 695
17-11 Offset 0100h: RCTCL - Root Complex Topology Capabilities List Register .................. 696
17-12 Offset 0104h: ESD - Element Self Description Register .......................................... 696
17-13 Offset 0110h: ULD - Upstream Link Description Register ........................................ 697
17-14 Offset 0118h: ULBA - Upstream Link Base Address Register ................................... 697
17-15 Offset 01A0h: ILCL - Internal Link Capabilities List Register.................................... 698
17-16 Offset 01A4h: LCAP - Link Capabilities Register .................................................... 698
17-17 Offset 01A8h: LCTL - Link Control Register .......................................................... 699
17-18 Offset 01AAh: LSTS - Link Status Register .......................................................... 700
17-19 Offset 3000h: TCTL - TCO Control Register .......................................................... 700
17-20 Offset 3100h: D31IP - Device 31 Interrupt Pin Register ........................................ 701
17-21 Offset 3108h: D29IP - Device 29 Interrupt Pin Register ........................................ 702
17-22 Offset 3140h: D31IR - Device 31 Interrupt Route Register .................................... 702
17-23 Offset 3144h: D29IR - Device 29 Interrupt Route Register .................................... 703
17-24 Offset 31FFh: OIC - Other Interrupt Control Register ............................................ 704
17-25 Offset 3400h: RC - RTC Configuration Register ..................................................... 704
17-26 Offset 3404h: HPTC - High Performance Precision Timer Configuration Register ........ 705
17-27 Offset 3410h: GCS - General Control and Status Register ...................................... 706
17-28 Offset 3414h: BUC - Backed Up Control Register .................................................. 708
17-29 Offset 3418h: FD - Function Disable Register ....................................................... 709
17-30 Offset 341Ch: PRC - Power Reduction Control Register Clock Gating ....................... 711
18-1 Bus 0, Device 31, Function 0: Summary of TCO Configuration Registers Mapped Through
TCOBASE I/O BAR“ ........................................................................................... 714
18-2 Offset 00h: TRLD - TCO Timer Reload and Current Value Register ......................... 715
18-3 Offset 02h: TDI - TCO Data In Register .............................................................. 715
18-4 Offset 03h: TDO - TCO Data Out Register .......................................................... 716
18-5 Offset 04h: TSTS1 - TCO 1 Status Register ........................................................ 716
18-6 Offset 06h: TSTS2 - TCO 2 STS Register ............................................................. 718
Intel^® EP80579 Integrated Processor Product Line Datasheet
66
August 2009
Order Number: 320066-003US