EP80579 Datasheet, PDF (658/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.6.1.4
Note:
Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address
Register
The upper address will not be used in the EP80579, which is limited to 32bit
addressing.
The Current Descriptor Upper Address Register (CDUAR) contains the upper 32-bit
address of the current chain descriptor in local system memory. This register is loaded
by the IMCH when a new chain descriptor is read.
Because the EP80579 supports 32 bit addressing only, this register needs to be set to
“0” at all times.
Table 16-300.Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 0Ch
Offset End: 0Fh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
Sticky
CDUAR0
Current Descriptor Address: The upper 32-bit local
system memory address of the current chain descriptor
that is read by the channel.
Bit Reset
Value
0000000h
Bit Access
RO
16.6.1.5
Offset 10h: SAR0 - Channel 0 Source Address Register
The Source Address Register (SAR) contains the lower 32-bit source address for the
current DMA transfer. This register is loaded by the IMCH when the source address field
of a new chain descriptor is read.
Table 16-301.Offset 10h: SAR0 - Channel 0 Source Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 10h
Offset End: 13h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
SAR0
Current Source Address: The lower 32-bit source
memory address for the current DMA transfer.
Sticky
Bit Reset
Value
0000000h
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
658
August 2009
Order Number: 320066-003US