EP80579 Datasheet, PDF (776/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
20.2.1.13 Offset 0Eh: DMA_CM - DMA Clear Mask Register
Table 20-16. Offset 0Eh: DMA_CM - DMA Clear Mask Register
Description:
View: IA F 1^a Base Address: 0000h (IO)
Offset Start: 0Eh
Offset End: 0Eh
View: IA F 1 Base Address: 0000h (IO)
Offset Start: 1Eh
Offset End: 1Eh
View: IA F 2^b Base Address: 0000h (IO)
Offset Start: DCh
Offset End: DCh
View: IA F 2 Base Address: 0000h (IO)
Offset Start: DDh
Offset End: DDh
Size: 8 bit
Default: XXXXXXXXh
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
07 : 00
CLMR
Clear Mask Register: Command enabled with a write to
the port.
a. View 1 describes the control registers for Channels 0-3.
b. View 2 describes the control registers for Channels 4-7.
Bit Reset
Value
X
Bit Access
WO
Intel^® EP80579 Integrated Processor Product Line Datasheet
776
August 2009
Order Number: 320066-003US