EP80579 Datasheet, PDF (953/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.2
USB (1.1) Controller I/O-Mapped Register Details
Some of the read/write register bits which deal with changing the state of the USB hub
ports function such that on read back they reflect the current state of the port and not
necessarily the state of the last write to the register. This allows the software to poll the
state of the port and wait until it is in the proper state before proceeding. A Host
controller reset, global reset, or port reset will immediately terminate a transfer on the
affected ports and disable the port. This affects the USBCMD register, bit [4] and the
PORTSC registers, bits [12,6,2]. See individual bit descriptions for more detail.
Base address for these I/O registers is set by the USBIOBAR register, see Section
25.1.1.9, “USBIOBAR - Base Address Register” on page 946.
Table 25-20. Summary of USB (1.1) Controller Configuration Registers Mapped Through
USBIOBAR I/O BAR
Offset Start Offset End
Register ID - Description
00h
02h
04h
06h
08h
0Ch
10h
12h
01h
03h
05h
07h
0Bh
0Ch
11h
13h
“USBCMD: USB Command Register” on page 954
“USBSTS: USB Status Register” on page 957
“USBINTR: USB Interrupt Enable Register” on page 959
“FRNUM: Frame Number Register” on page 959
“FRBASEADD: Frame List Base Address Register” on page 960
“SOFMOD: Start of Frame Modify Register” on page 961
“PSCR - Port Status and Control Register” on page 962
“PSCR - Port Status and Control Register” on page 962
Default
Value
0000h
0020h
0000h
0000h
XXXXX000h
40h
0080h
0080h
25.2.1
25.2.1.1
Register Details
USBCMD: USB Command Register
The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed. Table 25-22
provides additional information on the operation of the Run/Stop and Debug bits.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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