EP80579 Datasheet, PDF (439/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.45 Offset 88h: SDRC – DDR SDRAM Secondary Control Register
This register is used or setting memory controller parameters such as queue depths,
scheduler parameters, arbiter parameters, AIOC and IA-32 core stream enabling, IA-32
core parity checking, bank remapping, etc.
Table 16-49. Offset 88h: SDRC - DDR SDRAM Secondary Control Register (Sheet 1 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 88h
Offset End: 8Bh
Size: 32 bit
Default: 00000002h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
On Die Termination Enable: These bits enable the EP80579
on die termination. ODT control for the DQ[71:64]/DQS[8]
(ECC byte) buffers on the inbound read path.
Bit Reset
Value
Bit Access
31 :30
ODTZENA1
Encoding
00
01
10
Others
ODT
Disabled
60 ohms
120 ohms
Reserved
Y
00b
RW
On Die Termination Enable: These bits enable the EP80579
on die termination. ODT for the DQ[63:0]/DQS[7:0]
buffers on the inbound read path
29 :28
ODTZENA
Encoding
00
01
10
Others
ODT
Disabled
60 ohms
120 ohms
Reserved
Y
00b
RW
27 :26
Reserved Reserved
Y
00b
25 22
Reserved Reserved
N
0x0b
RW
Fuse Speed - Read only copy of the DDR speed fuse setting
00b - DDR-800 MTS
21 :20
FUSESPEED 01b - DDR-667 MTS
N
fuse
RO
10b - DDR-533 MTS
11b - DDR-400 MTS
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
439