EP80579 Datasheet, PDF (336/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
12.9.2.10 Next Descriptor Upper Address Register – NDUAR
The upper address will not be used in the EP80579, which is limited to 32-bit
addressing.
The Next Descriptor Upper Address Register (NDUAR) contains the upper 32-bit
address of the next descriptor chain in the local system memory. All address bits above
bit 35 must be zero or the transfer will abort and an error will be reported. A value of
zero implies the end of chain if the value of Next Descriptor Address (loaded into the
NDAR) is also zero. NDUAR is cleared to zero on power-on or system reset and is
loaded automatically with the Next Descriptor Upper Address field of the chain
descriptor (sixth DWord) when a new chain descriptor is read from memory. Application
software (likely the device driver) writes this register with the address of the first chain
descriptor in the memory prior to initiating a transfer.
Note:
The application software must make sure that the Start bit in the CCR and the Channel
Active bit in the CSR are clear prior to writing to the NDUAR. The IMCH protects this
register from being written when these bits are not clear. If the NDAR and NDUAR are
zero when the Start bit is set, no transfer will be initiated.
12.9.2.11 Transfer Count Register – TCR
The Transfer Count Register (TCR) contains the length of the current transfer in bytes.
The TCR is cleared to zero on power-on or system reset and is loaded automatically
with the Transfer Count field of the chain descriptor (seventh DWord) when a new chain
descriptor is read from memory. The TCR allows for a maximum transfer of 16 MB,
commensurate with current operating system capabilities. A value of zero is valid and
results in no data being transferred and no cycles generated on the source or
destination buses. It also results in completion bits being set after successful
completion “same as if it were a no zero length transfer”.
12.9.2.12 Descriptor Control Register – DCR
The Descriptor Control Register (DCR) contains control values for the transfer on a per
descriptor basis. The DCR is cleared to zero on power-on or system reset and is loaded
automatically with the Descriptor Control field of the chain descriptor (eighth DWord)
when a new chain descriptor is read from memory. The values in the DCR may vary for
different descriptors within a single chain.
Note:
The descriptor control register value stipulates coherence attributes for both the source
and destination addresses defined by this chain descriptor. Independent bits are also
defined to specify whether the source and destination address ranges are to be treated
as “coherent” or “non-coherent” by the IMCH. When the DCR value stipulates that one
or both of the source and destination are to be treated as “non-coherent” space, the
IMCH will rely on software to maintain system memory coherency and will not issue
FSB cycles during the block transfer to snoop processor caches on behalf of the
corresponding address range(s).
The following bits are defined in the CCR:
• Destination Address Mode: two bits specify destination address as increment or
constant
• Granularity of the transfer in destination constant address mode: two bits (1B, 2B,
or 4B)
• PCI-Express Destination Traffic Class: three bits define this traffic class
• Source Address Mode: two bits specify source address as increment, decrement, or
buffer/memory initialization
• Buffer/Memory Initialization Mode: Specifies a write to fill an area of memory
Intel^® EP80579 Integrated Processor Product Line Datasheet
336
August 2009
Order Number: 320066-003US