EP80579 Datasheet, PDF (655/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-297.Offset 00h: CCR0 - Channel 0 Channel Control Register (Sheet 3 of 3)
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 00h
Offset End: 03h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
00
Bit Acronym
Bit Description
Sticky
STRTDMA
Start:
0 = Cleared by the IMCH when the DMA transfer is
complete, when the DMA is stopped by software, or
when the DMA encounters any unrecoverable error.
The IMCH prevents this bit from being set when the
stopped or aborted bit is set in the CSR. The DMA
channel must be idle and software must clear the
CSR before starting the DMA channel with a new
descriptor chain.
1 = Channel is enabled for DMA transfer. Once set, this
bit cannot be cleared by software.
Bit Reset
Value
0b
Bit Access
RWS
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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