EP80579 Datasheet, PDF (1110/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 29-5. Offset 0Bh: RTC_REGB - Register B (General Configuration) (Sheet 2 of 2)
Description:
View: IA F
Base Address: RTC Standard RAM Bank
Offset Start: 0Bh
Offset End: 0Bh
Size: 8 bit
Default: X0X00XXXb
Power Well: RTC
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
DM
HOURFORM
DSE
Data Mode: The Data Mode (DM) bit specifies either
binary or BCD data representation.
0 = denotes BCD
1 = denotes binary
This bit is not affected by RSMRST# nor any other reset
signal.
Hour Format: This bit indicates the hour byte format.
0 = Twelve-hour mode is selected. In twelve hour mode,
the seventh bit represents AM as zero and PM as one.
1 = Twenty-four hour mode is selected.
This bit is not affected by RSMRST# nor any other reset
signal.
Daylight Savings Enable:
0 = Disabled
1 = Triggers two special hour updates per year when set
to one. One is on the first Sunday in April, where time
increments from 1:59:59 AM to 3:00:00 AM. The
other is the last Sunday in October when the time
first reaches 1:59:59 AM, it is changed to 1:00:00
AM. The time must increment normally for at least
two update cycles (seconds) previous to these
conditions for the time change to occur properly.
These special update conditions do not occur when
the DSE bit is set to zero. The days for the hour
adjustment are those specified in United States
federal law as of 1987, which is different than
previous years.
Note: This bit is not affected by RSMRST# nor any other
reset signal.
Bit Reset
Value
X
X
X
Bit Access
RW
RW
RW
29.3.1.3 Offset 0Ch: RTC_REGC - Register C (Flag Register)
Table 29-6. Offset 0Ch: RTC_REGC - Register C (Flag Register) (Sheet 1 of 2)
Description:
View: IA F
Base Address: RTC Standard RAM Bank
Offset Start: 0Ch
Offset End: 0Ch
Size: 8 bit
Default: 00X00000b
Power Well: RTC
Bit Range
07
Bit Acronym
Bit Description
Sticky
IRQF
Interrupt Request Flag: Interrupt Request Flag = (PF *
PIE) + (AF * AIE) + (UF *UFE). This also causes the RTC
Interrupt to be asserted.
Note: This bit is cleared upon RSMRST# or a read of
Register C.
Bit Reset
Value
0b
Bit Access
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
1110
August 2009
Order Number: 320066-003US