EP80579 Datasheet, PDF (434/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-46. Offset 64h: DRT1 - DRAM timing Register 1 (Sheet 4 of 4)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 64h
Offset End: 67h
Size: 32 bit
Default: 12110000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
2T or 1T timing on the command bus to DRAM devices.
Sticky
Bit Reset
Value
Bit Access
12 :12
2Tor1T
Encoding
0
1
Timing
1T
2T
N
0b
RW
Programmable NOP insertion:
Number of NOPs will be inserted between read/write
commands to slow down Membist activities in the same
11 :04
NOPCNT ^page.
N
00h
RW
Up to 255 clocks NOPs can be programmed to insert delay
between read/write commands. If NOPs delay is
programmable less than the required DRAM timing, Overall
NOP delay from command to command will not be seen.
Back-To-Back Write Turn Around: This field determines the
data bubble duration between write data bursts. It applies
to WR-WR pairs to different ranks, and is only expected to
be used in DDR2 mode with ODT enabled in the event that
ODT selections must change between ranks. The purpose
of this field is to control the data burst spacing on the DQ
bus.
The encoding below will be translated by the hardware into
a number of CMDCLK’s that will be inserted between read
write commands.
03 :01
BTBWTA
Encoding
000
001
010
011
100
101
110
111
Number of CMDCLK
delays
0
1
2
3
4
5
6
7
N
000b
RW
Bit[3] of the Programmable Read Pointer Delay field.
0 :0
PRGRPD_4 Please refer to DRT0[2:0] for more details on this bit field N
0b
RW
(Section 16.1.1.41).
Intel^® EP80579 Integrated Processor Product Line Datasheet
434
August 2009
Order Number: 320066-003US