EP80579 Datasheet, PDF (338/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 12-2. Interrupt Summary
Channel Status Register
(CSR) Flags
Interrupt Conditions
DCR Bit Settings
(INTR Enable Bits)
Stopped
Suspended
0
1
0²
-
-
-
1⁴
-
-
-
-
0
0²
1
1³
-
-
-
1
-
-
-
End of Transfer
1
-
-
1
-
-
-
-
1
-
-
End of Chain
0
-
-
1
1
-
-
-
-
1
-
Channel Abort¹
0
-
-
0
0
1
-
-
-
-
1
Notes:
1.
The IMCH ensures that any aborted transfer will be reported via the Channel Abort status bit and that
this bit will never be accompanied by an End of Transfer or End of Chain indication. This ensures that
software never mistakes an aborted transfer for a successfully completed transfer – even if the error
is not detected until the final write to the final destination address of the terminal chain descriptor.
2.
The Stop and Suspend functions are mutually exclusive, and only one of the two status bits will ever
be asserted by the IMCH. In the event that software asserts both controls in the CCR, the Stop
function will take precedence.
3.
The EDMA Suspend function causes the channel to suspend operation at the completion of the current
descriptor. The EOT status bit will always accompany the suspended status bit. Note that even if
interrupts are enabled for both EOT and suspend, only a single interrupt event will result.
4.
The Stop function causes the channel to abort the transfer in progress immediately. It is
recommended that software read back the channel status register to verify that a stop command has
taken effect, since this will be much faster than setting the interrupt enable for stop and waiting for
the interrupt to occur.
12.10.1
Interrupt Routing Mechanisms
Two different mechanisms are available to route interrupts generated by channels to
the IA-32 core. Note that the interrupt mechanism itself is not channel-specific; all
channels generating interrupts share the same interrupt vector and handler. This is in
line with the expectation that a single device driver controls each EDMA channel at
large, rather than independent drivers per channel.
The first interrupt mechanism uses the integrated IOxAPIC and 8259 emulation
hardware. All interrupts from the channels are logically OR’ed and routed to the
interface controller for propagation via the in-band Assert_Intx and Deassert_Intx
special cycles, emulating a level-sensitive interrupt output. The IMCH tracks these
special cycles, and forwards the signaled interrupt to the IA-32 core. If the APIC enable
bit is set, an interrupt will result in an APIC message. If the APIC enable bit is clear
(unanticipated but possible), an interrupt will result in a legacy mode 8259-style level
sensitive interrupt directly to the IA-32 core socket.
The second interrupt mechanism uses Message Signaled Interrupt (MSI) generation
functionality integrated into the EDMA. Internal interrupt messaging utilizes the PCI
message capability structure and does not support external interrupt input routing.
Intel^® EP80579 Integrated Processor Product Line Datasheet
338
August 2009
Order Number: 320066-003US