EP80579 Datasheet, PDF (410/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-27. Offset 9Dh: EXSMRC - Extended System Management RAM Control Register
(Sheet 2 of 3)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 9Dh
Offset End: 9Dh
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
06
05
04
03
Bit Acronym
Bit Description
Sticky
MDAP
APICDIS
Reserved
G_SMRAME
MDA Present: This bit works with the VGA Enable bits in
the BCTRL registers of Devices 2–3 to control the routing
of CPU initiated transactions targeting MDA compatible I/O
and memory address ranges. This bit should not be set if
none of the VGA Enable bits are set. If none of the VGA
enable bits are set, then accesses to IO address range
x3BCh-x3BFh are forwarded to NSI. If the VGA enable bit
is not set then accesses to IO address range x3BCh-x3BFh
are treated just like any other IO accesses. For example,
the cycles are forwarded to PEA[0:1] if the address is
within the corresponding IOBASE and IOLIMIT and ISA
enable bit is not set, otherwise they are forwarded to NSI.
Note: Since the logic performs the address decoding on
a DW boundary, the DW that includes the address
3BF also includes addresses 3BC, 3BD, and 3BE,
and accesses to any of these byte addresses are
handled as MDA references.
MDA resources are defined as the following:
Memory: 0B0000h - 0B7FFFh
I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(Including ISA address aliases, A[15:10] are not used in
decode)
Note: The VGA region includes I/O space ranges 3B0-
3BBh, and 3C0-3DFh, so there is an overlap
between these two I/O regions.
Any I/O reference that includes the I/O locations listed
above, or their aliases, are forwarded to NSI even if the
reference includes I/O locations not listed above.
The following table shows the behavior for all combinations
of MDA and VGA:
VGA MDA
0
0
0
1
1
0
1
1
Behavior
All References to MDA and VGA go to NSI
Illegal Combination (DO NOT USE)
All References to VGA go to device with VGA
enable set. MDA- only references
(I/O address
3BF and aliases) go to NSI.
VGA-only references go to the PCI
Express port
which has its VGA Enable bit set. MDA
references go to the NSI.
APIC Memory Range Disable:
0 = The IMCH send cycles between 0_FEC0_0000 and
0_FEC7_FFFF to NSI, accesses between 0_FEC8_0000
and 0_FEC8_0FFF are sent to PEA0, between
0_FEC8_1000 and 0_FEC8_1FFF are sent to PEA1B.
1 = The IMCH forwards all accesses to the IOAPIC regions
to NSI.
Reserved
Global SMRAM Enable:
0 = The Compatible SMRAM functions are disabled.
1 = The Compatible SMRAM functions are enabled,
providing 128 Kbyte of DRAM accessible at the
A0000h address while in SMM (ADS# with SMM
decode). To enable Extended SMRAM function this bit
has be set to 1. Refer to Section 16.1.1.26, “Offset
9Eh: SMRAM - System Management RAM Control
Register” for more details.
Once D_LCK (See Table 16-28) is set, this bit becomes
read-only.
Bit Reset
Value
0b
0b
0b
0b
Bit Access
RW
RW
RWL
Intel^® EP80579 Integrated Processor Product Line Datasheet
410
August 2009
Order Number: 320066-003US