EP80579 Datasheet, PDF (488/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-94. Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 8Ah
Offset End: 8Ah
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05 :04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Memory Test Complete SMI Enable: Generate SMI
when Bit 7 of DRAM_FERR or DRAM_NERR is set.
MTC_SMI _{0 = Disable}
N
1 = Enable
Poisoned Write to DRAM SMI Enable: Generate SMI
when Bit 6 of DRAM_FERR or DRAM_NERR is set.
PWD_SMI _{0 = Disable}
N
1 = Enable
Reserved Reserved
N
Error Threshold Detect SMI Enable: Generate SMI
when Bit 3 of DRAM_FERR or DRAM_NERR is set.
ETD_SMI _{0 = Disable}
N
1 = Enable
Scrubber Data Error SMI Enable: Generate SMI when
Bit 2 of DRAM_FERR or DRAM_NERR is set.
SDE_SMI _{0 = Disable}
N
1 = Enable
Uncorrectable Read Memory Error SMI Enable:
Generate SMI when Bit 1 of DRAM_FERR or DRAM_NERR is
URME_SMI ^set.
N
0 = Disable
1 = Enable
Correctable Read Memory Error SMI Enable: Generate
SMI when Bit 0 of DRAM_FERR or DRAM_NERR is set.
CRME_SMI _{0 = Disable}
N
1 = Enable
Bit Reset
Value
0b
0b
00b
0b
0b
0b
0b
Bit Access
RW
RW
RO
RW
RW
RW
RW
16.2.1.41 Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register
This register enables the memory controller to generate an SERR NSI special cycle for
various error flags. When an error flag is set in either the DRAM_FERR or DRAM_NERR
registers (see Section 16.2.1.36, “Offset 80h: DRAM_FERR - DRAM First Error Register”
and Section 16.2.1.37, “Offset 82h: DRAM_NERR - DRAM Next Error Register”),
hardware generates an SERR NSI special cycle when enabled in the DRAM_SERRCMD
register.
Note:
Software should enable one and only one message type for a given error flag.
Intel^® EP80579 Integrated Processor Product Line Datasheet
488
August 2009
Order Number: 320066-003US