EP80579 Datasheet, PDF (176/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
6.2.1
6.2.2
6.2.3
Memory Configuration
As described in the flow chart, one of the first actions of the BIOS is to configure main
memory. This section describes the memory configuration sequence of BIOS.
At reset the memory controller disables the output clock reference drivers for all DIMM
slots, which prevents them from locking at the wrong frequency, and then relocking
after this step in the initialization process.
Memory controller core logic boots at a factory set default frequency as is indicated by
the BSEL Pin. The BIOS must first set the DDR frequency and ratio via the DRC register
because the memory controller needs to re-lock itself at the desired DDR frequency.
BIOS configures the DDR frequency by reading the FSB frequency value from a
processor internal MSR and DDR2 circuitry and sets the DDR Speed bits [3:0] of the
DRC register (d0, f0, offset 7Ch).
Once the correct frequencies have been selected BIOS updates CKDIS (d0, f0, offset
8Ch), such that only populated ranks of populated DIMM slots receive output clocks
from the memory controller.
Using the DDR SPD data, BIOS programs the IMCH DRA and DRB registers for proper
translation of physical addresses to DDR row, bank, and column addresses.
BIOS further configures the DDR configuration, timing, and impedance compensation
settings to enable reliable communication between the IMCH and the DDR DIMM
devices. The DRT registers (d0, f0, offsets 78h and 64h) defaults settings can be found
in Section 11.0, “System Memory Controller”.
BIOS further performs DDR calibration, memory initialization, and optional MemBIST.
At this stage BIOS is aware of the total amount of memory populated in the system,
and may generate the starting value for the top of memory (TOM) register setting.
BIOS will generally want to complete at least a rudimentary memory test sequence
(next step) prior to finalizing the memory size information reported to the operating
system.
For memory initialization details refer to Section 11.0, “System Memory Controller”.
Wake from S3/S4/S5 are also described in the Figure 6-8
Memory Initialization
At this point in the boot sequence memory contains random data from power-on, and
would therefore generate non-deterministic ECC errors on read accesses. To zero-out
memory and initialize all locations with good ECC, the memory controller provides a
hardware engine which will walk all populated DRAM space issuing cache-line sized
writes with all zeroes as data.
Boot from Network
Booting from network on Intel platforms is supported by PXE. PXE (Preboot eXecution
Environment) is an existing open industry specification for network clients to
automatically download software images and configuration parameters. The PXE client
software is typically implemented as a BIOS Option ROM that is executed during the
preboot phase of the client system. This Option ROM (OpROM) implements a sufficient
network stack to perform all of the necessary network operations to boot an operating
system. This OpROM image is written assuming IA-32 architecture and instruction set.
Also, each OpROM image is modified specifically for a given Network Interface
Controller (NIC).
Intel^® EP80579 Integrated Processor Product Line Datasheet
176
August 2009
Order Number: 320066-003US