EP80579 Datasheet, PDF (279/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Note:
EDMA access is not permitted to the port, thus any address mapping to the legacy
interface will cause an abort.
Table 10-15. EDMA Accesses to Relocatable Address Spaces
Address
Space
NSI: M
NSI: PM
PEA: M[n]
PEA: PM[n]
NSI_SUB
PEA:
PM[n]
Conditions
-
Write, MAE = 1
Write, MAE = 0
Read Transaction
-
Write, MAE = 1
Write, MAE = 0
Read Transaction
Destination
IMCH Response
Abort
PEA[n]
Abort
Abort
Abort
PEA[n]
Abort
Abort
No support for EDMA destination on NSI
Transaction forwarded to destination PEA
port.
Abort. Memory access disabled.
Abort. No support for peer segment reads.
No support for EDMA destination on NSI
Transaction forwarded to destination PEA
port.
Abort. Memory access disabled.
Abort. No support for peer segment reads.
10.3
I/O Address Space
The IMCH generates outbound transactions on behalf of all IA-32 core I/O accesses.
The IMCH contains two internal registers in the IA-32 core I/O space dedicated to the
configuration access mechanism; the Configuration Address Register
(CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). The
behavior of the IMCH in response to accesses to these registers is described in
Chapter 13.0, “Platform Configuration.”
The IA-32 core allows 64 K+3 bytes to be addressed within the I/O space. The IMCH
propagates the IA-32 core I/O address without any translation to the targeted
destination bus. Note that the upper three locations can be accessed only during I/O
address wrap-around; when signal A16# is asserted on the processor bus. A16# is
asserted on the processor bus whenever a Dword I/O access is made from address
0FFFDh, 0FFFEh, or 0FFFFh. In addition, A16# is asserted when software attempts a
two-byte I/O access from address 0FFFFh.
All I/O accesses (read or write) which do not map to internal IMCH registers will receive
a DEFER response on the FSB, and be forwarded to the appropriate outbound port. The
IMCH never posts an I/O write.
The IMCH never responds to inbound transactions to I/O or configuration space
initiated on any port. Inbound I/O or configuration transactions requiring a completion
are terminated with “master abort” completion packets on the originating port
interface. Inbound I/O or configuration write transactions not requiring completion are
dropped.
10.3.1
Configuration Window
The I/O addresses 0CF8h and 0CFCh are treated specially, as they define the
compatible configuration window. Dword accesses to 0CF8h address the internal IMCH
configuration address register. Accesses from 1 to 4 bytes in size to the region from
0CFC-0CFFh are treated as configuration data accesses if configuration space is
enabled (bit31 of the configuration address register is set). Refer to Chapter 13.0,
“Platform Configuration.” for further details.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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