EP80579 Datasheet, PDF (24/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
23.3.4.1 Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register................ 866
23.3.4.2 Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register ...................... 867
23.3.4.3 Offset 128h: PxSSTS[0-1] – Port [0-1] Serial ATA Status Register ......... 868
23.3.4.4 Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register ........ 869
23.3.4.5 Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register ........... 870
23.3.4.6 Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register.......... 872
23.3.4.7 Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register ............... 872
23.3.4.8 Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register................ 873
23.4 Overview ........................................................................................................ 873
23.5 Legacy Operation............................................................................................. 873
23.5.1 Transfer Examples .................................................................................. 873
23.5.1.1 Register FIS Only ............................................................................ 873
23.5.1.2 Non-Queued DMA Data Transfers ...................................................... 874
23.5.1.3 SW Assisted Queued DMA Transfer .................................................... 875
23.5.2 Error Handling........................................................................................ 876
23.5.2.1 Errors on DMI ................................................................................. 876
23.5.2.2 Errors on SATA Interface .................................................................. 876
23.5.3 Hot Plug Operation ................................................................................. 878
23.5.4 48-Bit (“Large”) LBA Operation Requirements............................................. 878
23.5.5 Power Management Operation .................................................................. 879
23.5.5.1 Introduction ................................................................................... 879
23.5.5.2 Power State Mappings...................................................................... 879
23.5.5.3 Power State Transitions ................................................................... 880
23.5.5.4 SMI Trapping (APM) ........................................................................ 881
23.5.6 Interrupt Architecture ............................................................................. 882
23.5.7 Staggered Spin-up.................................................................................. 882
23.5.8 HW/SW Operation for Detecting an SATA Device Presence ........................... 882
23.5.8.1 Introduction ................................................................................... 882
23.5.8.2 Hardware Flow................................................................................ 882
23.5.8.3 Software Flow................................................................................. 883
23.5.9 SMI Generation ...................................................................................... 883
23.5.10 LED ...................................................................................................... 884
23.6 AHCI Operation ............................................................................................... 884
23.6.1 System Memory Structures ...................................................................... 884
23.6.2 Error Reporting and Recovery................................................................... 885
23.6.2.1 Error Types .................................................................................... 885
23.6.2.2 Error Recovery................................................................................ 888
23.6.3 Hot Plug Operation ................................................................................. 888
23.6.4 Power Management Operation .................................................................. 889
23.6.4.1 Introduction ................................................................................... 889
23.6.4.2 Power State Mappings...................................................................... 889
23.6.4.3 Power State Transitions ................................................................... 890
23.6.4.4 PME............................................................................................... 892
23.7 Additional Information ...................................................................................... 892
23.7.1 Mode Switching ...................................................................................... 892
23.7.1.1 AHCI Mode ..................................................................................... 893
23.7.1.2 IDE Mode ....................................................................................... 893
24.0 SMBus Controller Functional Description: Bus 0, Device 31, Function 3 ................. 895
24.1 Overview ........................................................................................................ 895
24.1.1 Host Controller ....................................................................................... 895
24.1.2 Slave Interface....................................................................................... 896
24.2 SMBus Controller PCI Configuration Register Details ............................................. 896
24.2.1 SMBus Controller PCI Configuration Register Descriptions ............................ 897
24.2.1.1
24.2.1.2
24.2.1.3
Offset 00h: VID: Vendor ID Register .................................................. 897
Offset 02h: DID: Device ID Register .................................................. 897
Offset 04h: CMD: Command Register................................................. 897
Intel^® EP80579 Integrated Processor Product Line Datasheet
24
August 2009
Order Number: 320066-003US