EP80579 Datasheet, PDF (489/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-95. Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 8Ch
Offset End: 8Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05 :04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Memory Test Complete SERR Enable: Generate SERR
when Bit7 of DRAM_FERR or DRAM_NERR is set.
MTC_SERR _{0 = Disable}
N
1 = Enable
Poisoned Write to DRAM SERR Enable: Generate SERR
when Bit 6 of DRAM_FERR or DRAM_NERR is set.
PWD_SERR _{0 = Disable}
N
1 = Enable
Reserved Reserved
N
Error Threshold Detect SERR Enable: Generate SERR
when Bit 3 of DRAM_FERR or DRAM_NERR is set.
ETD_SERR _{0 = Disable}
N
1 = Enable
Scrubber Data Error SERR Enable: Generate SERR
when Bit2 of DRAM_FERR or DRAM_NERR is set.
SDE_SERR _{0 = Disable}
N
1 = Enable
Uncorrectable Read Memory Error SERR Enable:
Generate SERR when Bit 1 of DRAM_FERR or DRAM_NERR
URME_SERR ^{is set.}
N
0 = Disable
1 = Enable
Correctable Read Memory Error SERR Enable:
Generate SERR when Bit 0 of DRAM_FERR or DRAM_NERR
CRME_SERR ^{is set.}
N
0 = Disable
1 = Enable
Bit Reset
Value
0b
0b
00b
0b
0b
0b
0b
Bit Access
RW
RW
RO
RW
RW
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
489