EP80579 Datasheet, PDF (366/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
14.2.1.8
PCI Express Errors and Errors on Behalf of PCI Express
IMCH-specific error detection, masking, and escalation mechanisms operate on a
parallel path to their standardized counterparts included in the PCI Express* Interface
Specification, Rev 1.0a. PCI Express errors are classified as either correctable or
uncorrectable. Uncorrectable errors are further broken down as fatal or non-fatal.
PCI Express specified correctable errors are logged in the Correctable Error Status
Register (Device 2-3, Function 0, Offset 110 - 113h), unless they are masked by a
corresponding bit in the Correctable Error Detect Mask Register (Device 2-3, Function
0, Offset 150-153h).
PCI Express specified uncorrectable errors are logged in the Uncorrectable Error Status
Register (Device 2-3, Function 0, Offset 104-107h), unless they are masked by a
corresponding bit in the Uncorrectable Error Detect Mask Register (Device 2-3,
Function 0, Offset 14C-14Fh). The Uncorrectable Error Severity Register (Device 2-3,
Function 0, Offset 10C - 10Fh) determines if bits in the Uncorrectable Status register
are treated as uncorrectable fatal or uncorrectable non-fatal errors. The Device Status
register (6Eh) bits are set when the corresponding category of bit is set in the
uncorrectable and correctable status registers.
Reporting of non-masked error bits to the root complex hierarchy of PCI Express error
registers is controlled on three different levels. Individual errors are masked for
reporting by the Uncorrectable Error Mask (Device 2-3, Function 0, Offset 108-10Bh)
and the Correctable Error Mask (Device 2-3, Function 0, Offset 114-117h) registers.
Individual error category (fatal, non-fatal, correctable, or unsupported) reporting is
enabled in the Device Control Register (Device 2-3, Function 0, Offset 6Ch) bits 3:0.
Finally, uncorrectable error reporting (fatal or non-fatal) reporting may also be enabled
by setting the SERR Enable bit in the PCI Command Register (Device 2-3, Function 0,
Offset 04-05h).
There is an error pointer, in the Advanced Error Capability and Control Register (Device
2-3, Function 0, Offset 118-11Bh) which will log the first uncorrectable error that is
enabled for reporting. Also some uncorrectable errors, when they are the first
uncorrectable error, will log their corresponding header log in the Header Log Registers
(Device 2-3, Function 0, Offset 11C-12Bh). An error pointer for unmasked correctable
errors has been added in the Error Do Command Register (Device 2-3, Function 0,
Offset 148-14Bh).
These internally detected errors when they are reported are referred to as virtual error
messages. These are different from errors which are detected by the downstream
device which then sends an error message to the root complex, which are referred to
as externally detected or “received’ error messages. The received system error bit in
the Secondary Status Register (Device 2-3, Function 0, Offset 1E-1F) is set when either
fatal or non-fatal messages are received at the root complex.
At this point in the PCI Express error hierarchy, these virtual error messages are
logically ORed with the received error messages, and will just be referred to as fatal,
non-fatal, or correctable error messages, no reference to either virtual or received.
When enabled by the enable system error bit in the PCI Command Register, any fatal or
non-fatal messages will set the signaled system error bit in the PCI Status register
(Device 2-3, Function 0, Offset 06-07h). The Root Port Error Message Status Register
(Device 2-3, Function 0, Offset 130-133h) will indicate first and multiple errors of each
error message category, and the corresponding error source IDs of the first correctable
and uncorrectable error messages will be the logged in the Error Source ID register
(134h).
These errors that have been reported to the root complex can now be reported to the
system, via the category enables in the Root Port Error Command Register (Device 2-3,
Function 0, Offset 12C-12Fh) for interrupts. These interrupts can be in the form of
Intel^® EP80579 Integrated Processor Product Line Datasheet
366
August 2009
Order Number: 320066-003US