EP80579 Datasheet, PDF (1143/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
30.5.3
frame was driven by the peripheral in this mode, the IICH drives the SERIRQ line low
for one PCI clock less than in continuous mode. This mode of operation allows for a
quiet, and therefore lower power, operation.
Data Frames
Once the Start frame has been initiated, the SERIRQ peripherals start counting frames
based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly three
phases of one clock each. The three phases are:
• Sample Phase: During this phase, the SERIRQ device drives SERIRQ low if the
corresponding interrupt signal is low. If the corresponding interrupt is high, then
the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due
to pull-up resistors (there is no internal pull-up resistor on this signal, an external
pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames
indicates that an active-high ISA (legacy) interrupt is not being requested, but a
low level during the PCI INT[A:D], SMI#, and ISA (legacy) IOCHK# frame indicates
that an active-low interrupt is being requested.
• Recovery Phase: During this phase, the device drives the SERIRQ line high if in
the Sample Phase it was driven low. If it was not driven in the sample phase, it is
tri-stated in this phase.
• Turn-around Phase: The device tri-states SERIRQ.
30.5.4
Stop Frame
After all the data frames, a Stop Frame is driven by the IICH. The SERIRQ signal is
driven low for two or three PCI clocks. The number of clocks is determined by the
SERIRQ configuration register (SCNT.MD field in D31, F0 configuration space). The
number of clocks determines the next mode as shown in Table 30-29.
Table 30-29. Stop Frame Definition
Stop Frame Width Next Mode
2 PCI clocks
3 PCI clocks
Quite Mode: Any SERIRQ device initiates a Start Frame
Continuous Mode: Only the IICH may initiate a Start Frame
30.5.5
Serial Interrupts Not Supported via SERIRQ
There are three interrupts seen through the serial stream that are not supported by the
IICH. These interrupts are generated internally, and are not sharable with other devices
within the system. These interrupts are:
• IRQ0:Heartbeat interrupt generated off of the internal 8254 counter 0.
• IRQ8#:RTC interrupt can only be generated internally.
• IRQ13:..... Floating point error interrupt generated off of the processor assertion of
FERR#.
The IICH ignores the state of these interrupts in the serial stream, and does not adjust
their level based on the level seen in the serial stream.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1143