EP80579 Datasheet, PDF (937/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 24-57. Slave Read Cycle Format
Bit
Description
1
2–8
9
10
Start
Slave Address - 7 bits
Write
ACK
11 – 18 Command code - 8 bits
Driven by:
External Microcontroller
External Microcontroller
External Microcontroller
CMI
External Microcontroller
19 ACK
20 Repeated Start
21 – 27 Slave Address - 7 bits
28 Read
29 ACK
30 – 37 Data Byte
CMI
External Microcontroller
External Microcontroller
External Microcontroller
CMI
CMI
38 NOT ACK
39 Stop
External Microcontroller
External Microcontroller
Comment:
Must match value in Receive Slave Address register
Hardwired to 0
Indicates which register is being accessed. See Table 24-58
for list of implemented registers.
Must match value in Receive Slave Address register
Hardwired to 1
Value depends on register being accessed. See Table 24-58
for list of implemented registers.
Table 24-58. Data Values for Slave Read Registers (Sheet 1 of 2)
Register
0
1
2
3
Bits
07:00
02:00
07:03
03:00
07:04
05:00
07:06
Description
Reserved for capabilities indication. Should always return 00h. Future chips may return
another value to indicate different capabilities.
System Power State
000 = S0
001 = Reserved
010 = Reserved
011 = S3
100 = Reserved
101 = S5
110 = Reserved
111 = Reserved
Reserved
Reserved
Reserved
Watchdog Timer current value. Watchdog Timer has 10 bits, but this field is only 6 bits. If the
current value is greater than 3Fh, the CMI always reports 3Fh in this field.
Reserved
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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