EP80579 Datasheet, PDF (957/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
25.2.1.2
USBSTS: USB Status Register
This register indicates pending interrupts and various states of the Host Controller. The
status resulting from a transaction on the serial bus is not indicated in this register.
Software sets a bit to 0 in this register by writing a 1 to it. See Section 4, “Interrupts,”
of the Universal Host Controller Interface (UHCI) Specification, Rev. 1.1, for additional
information concerning USB interrupt conditions.
Table 25-23. USBSTS: USB Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: USBIOBAR (IO)
Bus:Device:Function: 0:29:0
Offset Start: 02h
Offset End: 03h
Size: 16 bit
Default: 0020h
Power Well: Core
Bit Range
15 : 06
05
04
03
Bit Acronym
Bit Description
Sticky
Reserved
HCH
HCPE
HSE
Reserved
HCHalted:
0 = The host controller is running.
1 = The host controller has stopped executing as a
result of the Run/Stop bit being set to 0, either by
software or by the host controller hardware (debug
mode or an internal error). Default.
Software clears this bit by writing a 1 to it.
Host Controller Process Error:
0 = No error.
1 = The host controller has detected a fatal error. This
indicates that the Host Controller suffered a
consistency check failure while processing a
Transfer Descriptor. An example of a consistency
check failure would be finding an illegal PID field
while processing the packet header portion of the
TD. When this error occurs, the Host Controller
clears the Run/Stop bit in the Command register to
prevent further schedule execution. A hardware
interrupt is generated to the system.
Software clears this bit by writing a 1 to it.
Host System Error:
0 = No error occurred.
1 = A serious error occurs during a host system access
involving the Host Controller module. Conditions
that set this bit to 1 include Parity error, Master
Abort, and Target Abort. When this error occurs,
the Host Controller clears the Run/Stop bit in the
Command register to prevent further execution of
the scheduled TDs. A hardware interrupt is
generated to the system.
Software clears this bit by writing a 1 to it.
Bit Reset
Value
0h
1
0h
0h
Bit Access
RO
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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