EP80579 Datasheet, PDF (34/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
Acceleration and I/O Complex, Volume 4 of 6 ........................... 1213
34.0 PCI-to-PCI Bridge ................................................................................................ 1215
34.1 Summary ..................................................................................................... 1215
34.2 PCI-to-PCI Bridge Detailed Register Descriptions................................................ 1215
34.2.1 PCI-to-PCI Bridge Header ...................................................................... 1216
34.2.2 PCI-to-PCI Bridge Configuration Space .................................................... 1217
34.2.2.1
34.2.2.2
34.2.2.3
34.2.2.4
34.2.2.5
34.2.2.6
34.2.2.7
34.2.2.8
34.2.2.9
34.2.2.10
34.2.2.11
34.2.2.12
34.2.2.13
34.2.2.14
34.2.2.15
34.2.2.16
34.2.2.17
34.2.2.18
34.2.2.19
34.2.2.20
34.2.2.21
34.2.2.22
34.2.2.23
34.2.2.24
34.2.2.25
34.2.2.26
34.2.2.27
34.2.2.28
34.2.2.29
34.2.2.30
34.2.2.31
34.2.2.32
34.2.2.33
34.2.2.34
34.2.2.35
Offset 0h: VID – Vendor Identification Register ................................. 1217
Offset 2h: DID – Device Identification Register.................................. 1217
Offset 4h: PCICMD – Device Command Register ................................ 1217
Offset 6h: PCISTS – Device Status Register ...................................... 1218
Offset 8h: RID – Revision ID Register .............................................. 1219
Offset 9h: CC – Class Code Register ................................................ 1219
Offset Ch: CLS – Cacheline Size Register .......................................... 1219
Offset Dh: LT – Latency Timer Register ............................................ 1220
Offset Eh: HDR – Header Type Register............................................ 1220
Offset 10h: CSRBAR0 – Control and Status Registers Base Address Register
1220
Offset 14h: CSRBAR1 – Control and Status Registers Base Address Register
1221
Offset 18h: PBNUM – Primary Bus Number Register ........................... 1221
Offset 19h: SECBNM – Secondary Bus Number Register ..................... 1221
Offset 1Ah: SUBBNM – Subordinate Bus Number Register................... 1222
Offset 1Bh: SECLT – Secondary Latency Timer Register...................... 1222
Offset 1Ch: IOB – I/O Base Register ................................................ 1222
Offset 1Dh: IOL – I/O Limit Register ................................................ 1223
Offset 1Eh: SECSTA – Secondary Status Register .............................. 1223
Offset 20h: MEMB – Memory Base Register....................................... 1224
Offset 22h: MEML – Memory Limit Register ....................................... 1224
Offset 24h: PMBASE – Prefetchable Memory Base Register.................. 1225
Offset 26h: PMLIMIT – Prefetchable Memory Limit Register ................. 1225
Offset 28h: PMBASU – Prefetchable Memory Base Upper Register ........ 1226
Offset 2Ch: PMLMTU – Prefetchable Memory Limit Upper Register ........ 1226
Offset 30h: IOBU – I/O Base Upper Register ..................................... 1227
Offset 32h: IOLU – I/O Limit Upper Register ..................................... 1227
Offset 34h: CP – Capabilities Pointer Register.................................... 1227
Offset 3Ch: IRQL – Interrupt Line Register........................................ 1228
Offset 3Dh: IRQP – Interrupt Pin Register......................................... 1228
Offset 3Eh: BCTL – Bridge Control Register....................................... 1228
Offset DCh: PCID – Power Management Capability ID Register ............ 1229
Offset DDh: PCP – Power Management Next Capability Pointer
Register ....................................................................................... 1230
Offset DEh: PMCAP – Power Management Capability Register .............. 1230
Offset E0h: PMCS – Power Management Control and Status
Register ....................................................................................... 1231
Offset E2h: PMCSE – Power Management Control and Status Extension
Register ....................................................................................... 1232
35.0 PCI-to-PCI Bridge: AIOC Configuration ............................................................... 1233
35.1 Overview ...................................................................................................... 1233
35.2 Feature List .................................................................................................. 1233
35.3 PCI Configuration Registers............................................................................. 1233
35.3.1 Description of PCI Configuration Header Space ......................................... 1233
35.4 Interrupt Handling for AIOC Devices................................................................. 1235
35.5 Power Management of AIOC Devices ................................................................ 1236
35.6 Gigabit Ethernet MAC Configuration Spaces: Bus M, Device 0-2, Function 0 ........... 1237
35.6.1 Register Details .................................................................................... 1237
35.6.1.1 Offset 00h: VID – Vendor Identification Register................................ 1240
35.6.1.2 Offset 02h: DID – Device Identification Register ................................ 1241
Intel^® EP80579 Integrated Processor Product Line Datasheet
34
August 2009
Order Number: 320066-003US