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EP80579 Datasheet, PDF (1238/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line | |||
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Intel® EP80579 Integrated Processor
Table 35-3. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 2 of 2)
Offset Start Offset End
Register ID - Description
Default
Value
F1h
F1h
âOffset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Registerâ on
page 1258
00h
F2h
F3h
âOffset F2h: MCTL: Message Signalled Interrupt Control Registerâ on page 1259 0000h
F4h
F7h
âOffset F4h: MADR: Message Signalled Interrupt Address Registerâ on page 1259 00000000h
F8h
F9h
âOffset F8h: MDATA: Message Signalled Interrupt Data Registerâ on page 1260 0000h
Table 35-4. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 1 of 2)
Offset Start Offset End
Register ID - Description
00h
02h
04h
06h
08h
09h
0Eh
10h
14h
2Ch
2Eh
34h
3Ch
3Dh
DCh
DDh
DEh
E0h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
01h
03h
05h
07h
08h
0Bh
0Eh
13h
17h
2Dh
2Fh
34h
3Ch
3Dh
DCh
DDh
DFh
E1h
E4h
E5h
E6h
E7h
E8h
ECh
F0h
âOffset 00h: VID: Vendor Identification Registerâ on page 1241
âOffset 02h: DID: Device Identification Registerâ on page 1242
âOffset 04h: PCICMD: Device Command Registerâ on page 1243
âOffset 06h: PCISTS: PCI Device Status Registerâ on page 1244
âOffset 08h: RID: Revision ID Registerâ on page 1245
âOffset 09h: CC: Class Code Registerâ on page 1245
âOffset 0Eh: HDR: Header Type Registerâ on page 1246
âOffset 10h: CSRBAR: Control and Status Registers Base Address Registerâ on
page 1246
âOffset 14h: IOBAR: CSR I/O Mapped BAR Registerâ on page 1247
âOffset 2Ch: SVID: Subsystem Vendor ID Registerâ on page 1248
âOffset 2Eh: SID: Subsystem ID Registerâ on page 1248
âOffset 34h: CP: Capabilities Pointer Registerâ on page 1249
âOffset 3Ch: IRQL: Interrupt Line Registerâ on page 1249
âOffset 3Dh: IRQP: Interrupt Pin Registerâ on page 1250
âOffset DCh: PCID: Power Management Capability ID Registerâ on page 1251
âOffset DDh: PCP: Power Management Next Capability Pointer Registerâ on
page 1251
âOffset DEh: PMCAP: Power Management Capability Registerâ on page 1252
âOffset E0h: PMCS: Power Management Control and Status Registerâ on
page 1253
âOffset E4h: SCID: Signal Target Capability ID Registerâ on page 1254
âOffset E5h: SCP: Signal Target Next Capability Pointer Registerâ on page 1254
âOffset E6h: SBC: Signal Target Byte Count Registerâ on page 1255
âOffset E7h: STYP: Signal Target Capability Type Registerâ on page 1255
âOffset E8h: SMIA: Signal Target IA Mask Registerâ on page 1256
âOffset ECh: SINT: Signal Target Raw Interrupt Registerâ on page 1257
âOffset F0h: MCID: Message Signalled Interrupt Capability ID Registerâ on
page 1258
Default
Value
8086h
5044h
0000h
10h
Variable
020000h
00h
00000000h
00000001h
0000h
0000h
DCh
00h
01h
01h
E4h
X023h
0000h
09h
F0h
09h
01h
0h
00h
05h
Intel® EP80579 Integrated Processor Product Line Datasheet
1238
August 2009
Order Number: 320066-003US
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