EP80579 Datasheet, PDF (574/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.4.1.60 Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register
The Uncorrectable Error Mask register controls reporting of individual errors by device
to the PCI Express* Root Complex via a PCI Express* error message. A masked error
(respective bit set in mask register) is not reported to the PCI Express Root Complex by
an individual device. However, masked errors are still logged in the Uncorrectable Error
Status register. There is one mask bit corresponding to every implemented bit in the
Uncorrectable Error Status register. These bits are sticky through reset.
Table 16-199.Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 108h
Offset End: 10Bh
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 108h
Offset End: 10Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
31 : 21
20
19
18
17
16
15
14
13
12
11 : 05
04
03 : 00
Reserved Reserved
Unsupported Request:
USR_UNCERRM
SK
0
=
Report Unsupported Request Error
1 = Mask Unsupported Request Error
EEM
ECRC Error Mask:
Note: ECRC is not supported for the EP80579.
MTM
Malformed TLP Mask:
0 = Report Malformed TLP Error
1 = Mask Malformed TLP Error
ROM
Receiver Overflow Mask: Optional PCI Express*
specification bit, implemented for.
0 = Report Receiver Overflow Error
1 = Mask Receiver Overflow Error
UCM
Unexpected Completion Mask :
0 = Report Receiver Overflow Error
1 = Mask Receiver Overflow Error
CAM
Completer Abort Mask: Optional PCI Express*
specification bit, implemented for.
0 = Report Completer Abort Error
1 = Mask Completer Abort Error
CTM
Completion Timeout Mask:
0 = Report Completion Timeout Error
1 = Mask Completion Timeout Error
FCPEM
Flow Control Protocol Error Mask: Optional PCI
Express* specification bit, implemented for.
0 = Report Flow Control Protocol Error
1 = Mask Flow Control Protocol Error
PTM
Poisoned TLP Mask:
0 = Report Poisoned TLP Error
1 = Mask Poisoned TLP Error
Reserved Reserved
DLPEM
Data Link Protocol Error Mask:
0 = Report Data Link Protocol Error
1 = Mask Data Link Protocol Error
Reserved Reserved
Sticky
Bit Reset
Value
000h
Bit Access
Y
0b
RW
Y
0b
RO
Y
0b
RW
Y
0b
RW
Y
0b
RW
Y
0b
RW
Y
0b
RW
Y
0b
RW
Y
0b
RW
00h
Y
0b
RW
000b
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
574
August 2009
Order Number: 320066-003US