EP80579 Datasheet, PDF (1669/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.30 Offset 0200h: L2_EtherType - L2 EtherType Register
Register
Name
L2_EtherType
Access
(See below.) Reset Value x0000_88F7
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Reserved)
EtherType
02
Table 41-40. Offset 0200h: L2 EtherType Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000200h
Offset End: 00000203h
Size: 32 bits
Default: 000088F7h
Power Well: Core
Bit Range
31 : 16
15 : 0
Bit Acronym
Bit Description
Sticky
RSVD
EtherType
Reserved for future use.
Must be written as ‘0’
Ethertype compare value (default = 0x88F7). The user
may optionally supply a different Ethertype compare value
for L2 IEEE1588 detection
Bit Reset
Value
0
88F7h
Bit Access
RO
RW
41.6.1.31 Offset 0204h: UD_EtherType - User Defined EtherType Register
Register
Name
UD_EtherType
Access
(See below.) Reset Value x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Mask
UD_EtherType
Table 41-41. Offset 0204h: User Defined EtherType Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 0000204h
Offset End: 0000207h
Size: 32 bits
Default: 00000000h
Power Well: Core
Bit Range
31 : 16
15 : 0
Bit Acronym
Bit Description
Mask
Mask for compare value
UD_EtherType
User defined compare value for ethertype field. Used in
conjunction with mask, above.
Sticky
Bit Reset
Value
0h
0h
Bit Access
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1669