EP80579 Datasheet, PDF (1741/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
48.4.2.3 PCI Express*
Table 48-9. PCI Express Interface Signals (Sheet 1 of 4)
Signal Name
PEA0_Tp[0]
PEA0_Tn[0]
PEA0_Rp[0]
PEA0_Rn[0]
PEA0_Tp[1]
PEA0_Tn[1]
IO Type
LV Diff
LV Diff
LV Diff
LV Diff
LV Diff
LV Diff
Direction
Ball
Count
O
1
O
1
I
1
I
1
O
1
O
1
External
Pull-Up/
Down
[Ohms]
BSC/
XOR
Signal Description Normal/Alternate Mode
PCI Express Interface Port A Transmit Data Pair
(Differential): The positive side of the PCI
Express Port A transmit data pair. These signals
are an output (Tx) from the EP80579’s
perspective, and must be connected to the input
(receive or Rx) signals of the other PCI Express
device.
XOR
The signals for this 1x8 interface can be trained
to 2x4 or 2x1 ports. These port configurations
map to signals as follows (y is either "n" or "p"):
XOR
1x8 Interface Configuration:
- PEA0_Ty[7:0] = Link 0
2x4 Interface Configuration:
- PEA1_Ty[7:4] = Link 1
- PEA0_Ty[3:0] = Link 0
2x1 Interface Configuration:
- PEA1_Ty[4] = Link 1
- PEA0_Ty[0] = Link 0
PCI Express Interface Port A Transmit Data Pair
(Differential): The negative side of the PCI
Express Port A transmit data pair (see
PEA0_Tp[0]).
PCI Express Interface Port A Receive Data Pair
(Differential): The positive side of the PCI
Express Port A receive data pair. These signals
are an input (Rx) from the EP80579’s
perspective, and must be connected to the
output (transmit or Tx) signals of the other PCI
Express device.
XOR
The signals for this 1x8 interface can be trained
to 2x4 or 2x1 ports. These port configurations
map to signals as follows (y is either "n" or "p"):
XOR
XOR
XOR
1x8 Interface Configuration:
- PEA0_Ry[7:0] = Link 0
2x4 Interface Configuration:
- PEA1_Ry[7:4] = Link 1,
- PEA0_Ry[3:0] = Link 0
2x1 Interface Configuration:
- PEA1_Ry[4] = Link 1,
- PEA0_Ry[0] = Link 0
PCI Express Interface Port A Receive Data Pair
(Differential): The negative side of the PCI
Express Port A receive data pair (see
PEA0_Rp[0]).
PCI Express Interface Port A Transmit Data Pair
(Differential): The positive side of the PCI
Express Port A transmit data pair (see
PEA0_Tp[0]).
PCI Express Interface Port A Transmit Data Pair
(Differential): The negative side of the PCI
Express Port A transmit data pair (see
PEA0_Tn[0])
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1741