EP80579 Datasheet, PDF (1353/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.5.2.1
37.5.2.2
37.5.2.3
37.5.3
37.5.3.1
Note:
Interrupt Cause Set/Read Registers
The read register records the cause of the interrupt. All bits set at the time of the read
are auto-cleared. The cause bit is set for each bit written as one in the set register. If
there is a race between hardware setting a cause and software clearing an interrupt,
the bit remains set. No race condition exists on writing the set register. Set provides for
software posting of an interrupt. Reads are auto-cleared to avoid expensive write
operations. Most systems have write buffering that minimizes overhead, but this
typically requires a read operation to guarantee that the write has been flushed from
posted buffers. Without auto-clear, the cost of clearing an interrupt can be as high as
two reads and one write.
Interrupt Mask Set (Read)/Clear Registers
Interrupts appear only if the interrupt cause bit is a one and the corresponding
interrupt mask bit is a one. Software blocks assertion of the interrupt wire by clearing
the bit in the mask register. The cause bit stores the interrupt event regardless of the
state of the mask bit. Clear and set make this register more “thread safe” by avoiding a
read-modify-write operation on the mask register. The mask bit is set for each bit
written to a one in the set register and cleared for each bit written in the clear register.
Reading the set register returns the current value.
Interrupt Throttling Register
The frequency of functional interrupts from the network controller can be reduced when
inter-interrupt interval value is non-zero. Controller asserts pending interrupts only at
regularly scheduled intervals. When inter-interrupt interval value is zero, controller
asserts pending interrupts immediately.
The Interrupt throttling register only applies to the GbE functional interrupt 0.
Hardware Acceleration Capability
The GbE provides CPU off loading capabilities. The functionality provided by these
features may significantly reduce CPU utilization by shifting the burden of the functions
from the driver to the hardware.
These features include:
• Receive & Transmit Checksum Off loading
• TCP Segmentation
These functions are covered in more detail in “Receive Packet Checksum Off loading”
on page 1363, “Transmit Checksum Off loading” on page 1379, and “TCP
Segmentation” on page 1380. The following sections provide a brief overview of these
capabilities.
Checksum Off-Loading
The GbE provides the ability to off load the IPv4, TCP & UDP checksum requirements
from the software device driver. For common frame types, the hardware automatically
calculates, inserts and checks the appropriate checksum values typically handled by
software.
IPv6 headers do not have a checksum.
For transmits where the device is doing non-TCP segmentation, every transmitted
Ethernet packet may have two checksums calculated and inserted by the device.
Typically these would be the IPv4 and either TCP or UDP checksums. The driver
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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