EP80579 Datasheet, PDF (1650/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
41.6.1.10 Offset 0024h: TS_SysTimeHi - System Time High Register
Register
Name
TS_SysTimeHi
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SystemTime_High[31:0]
Table 41-20. Offset 0024h: TS_SysTimeHi Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000024h
Offset End: 00000027h
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range
31 : 0
Bit Acronym
Bit Description
Sticky
This register contains the upper 32 bits of system time.
SystemTime_Hi
gh
When the user wants to read or write the system time,
this register must first access the SystemTime_Low
Register. See “System Time Low Register” on page 4784
for more details.
Bit Reset
Value
0000h
Bit Access
RW
41.6.1.11 Offset 0028h: TS_TrgtLo - Target Time Low Register
Register
Name
TS_TrgtLo
Access
(See below.) Reset Value 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TargetTime_Low[31:0]
Table 41-21. Offset 0028h: TS_TrgtLo Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000028h
Offset End: 0000002Bh
Size: 32 bits
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 : 0
The Target Time register set contains 64 bits of a time
value. When the system time is greater than or equal to
the target time value, an interrupt is generated to the
TargetTime_Low Host on the ts_intreq signal if the ttm bit in the Time
Sync Control register is set.
For more information about the Target Time interrupt, see
“Time Sync Control Register” on page 4775.
Bit Reset
Value
0000h
Bit Access
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1650
August 2009
Order Number: 320066-003US