EP80579 Datasheet, PDF (32/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
30.5.6 Special Notes on IRQ14 and IRQ15 ......................................................... 1144
30.5.7 Data Frame Format............................................................................... 1144
31.0 8254 Timers......................................................................................................... 1145
31.1 Overview ...................................................................................................... 1145
31.2 8254 Timer I/O-Mapped Register Details........................................................... 1145
31.2.1 Timer Registers .................................................................................... 1146
31.2.1.1
31.2.1.2
31.2.1.3
Offset 43h: TCW - Timer Control Word Register................................. 1146
Offset 40h: TSB[0-2] - Interval Timer Status Byte Format
Register ....................................................................................... 1146
Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports
Register ....................................................................................... 1148
31.3 Counters ...................................................................................................... 1148
31.3.1 Counter 0, System Timer....................................................................... 1148
31.3.2 Counter 1, Refresh Request Signal .......................................................... 1148
31.3.3 Counter 2, Speaker Tone ....................................................................... 1148
31.3.4 Counter Operating Modes ...................................................................... 1149
31.4 Timer Programming ....................................................................................... 1149
31.5 Reading from the Interval Timer ...................................................................... 1150
31.5.1 Simple Read ........................................................................................ 1150
31.5.2 Counter Latch Command ....................................................................... 1150
31.5.3 Read Back Command ............................................................................ 1151
32.0 High Precision Event Timers................................................................................. 1153
32.1 Overview ...................................................................................................... 1153
32.2 Register Details ............................................................................................. 1153
32.2.1 Register Descriptions ............................................................................ 1155
32.2.1.1
32.2.1.2
32.2.1.3
32.2.1.4
32.2.1.5
32.2.1.6
Offset 000h: GCAP_ID - General Capabilities and ID Register .............. 1155
Offset 010h: GEN_CONF - General Configuration Register................... 1156
Offset 020h: GINTR_STA - General Interrupt Status Register .............. 1157
Offset 0F0h: MAIN_CNT - Main Counter Value Register....................... 1158
Offset 100h: HPTCC[0-2] - Timer n Configuration and
Capabilities Register ...................................................................... 1159
Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register ........... 1161
32.3 Theory Of Operation....................................................................................... 1164
32.3.1 Timer Accuracy Rules ............................................................................ 1164
32.3.2 Interrupt Mapping................................................................................. 1164
32.3.3 Periodic vs. Non-Periodic Modes.............................................................. 1165
32.3.3.1 Non-Periodic Mode ........................................................................ 1165
32.3.3.2 Periodic Mode ............................................................................... 1165
32.3.4 Enabling the Timers ............................................................................. 1166
32.3.5 Interrupt Levels.................................................................................... 1166
32.3.6 Handling Interrupts............................................................................... 1166
32.3.7 Unloading Device Driver Issues .............................................................. 1167
33.0 Serial I/O Unit and Watchdog Timer .................................................................... 1169
33.1 Overview ...................................................................................................... 1169
33.2 Features ....................................................................................................... 1169
33.3 Functional Description .................................................................................... 1170
33.3.1 Host Processor Interface (LPC) ............................................................... 1170
33.4 LPC Interface ................................................................................................ 1170
33.4.1 LPC Cycles........................................................................................... 1170
33.4.1.1 I/O Read and Write Cycles.............................................................. 1171
33.4.2 Policy.................................................................................................. 1171
33.4.3 LPC Transfers....................................................................................... 1171
33.4.3.1 I/O Transfers ................................................................................ 1171
33.5 Logical Devices 4 and 5: Serial Ports (UART1 and UART2) ................................... 1171
Intel^® EP80579 Integrated Processor Product Line Datasheet
32
August 2009
Order Number: 320066-003US