EP80579 Datasheet, PDF (438/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-48. Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register (Sheet 2
of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 84h
Offset End: 87h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
18 18
17 :16
15 : 00
Bit Acronym
Bit Description
Sticky
Memory Poison Enable: Allows for propagation of data
errors not initiated by this feature to DRAM. Error injection
via bit 20 is possible regardless of this bit setting.
The setting of this bit has no effect on the reporting or
logging of data errors.
MEMPEN ^{0 = Error poisoning is disabled, data errors are not}
N
propagated, meaning that only good ECC is generated
ECC mode even when bad parity is detected on its
interface.
1 = Error poisoning enabled when in ECC mode. The
memory controller will poison the write data to DRAM
when it detects a parity error on its interface.
DPRSL
Data pair selector: This two-bit field selects which pair of
quad-words in a cache line the inversion vector is applied
against. Regardless of what operational mode the memory
subsystem is in, this field always applies to the same QW
pair. QW0 corresponds to data bits 63:00, QW1 to
[127:64] … and QW7 corresponds to [511:448]
N
00 QW0 and QW1
01 QW2 and QW3
10 QW4 and QW5
11 QW6 and QW7
ECC bit invert vector: This vector operates individually
for every ECC bit in the selected High or Low ECC block,
during writes to DRAM.
For all k between 0 and 15, when bit (k) set to 1, the value
of the k ECC bit (which corresponds with the k data byte
lane) is inverted. Otherwise, the value the k ECC bit is not
affected.
In other words, bits 15:08 are applied to the ECC vector of
ECCBIN the high Qword in the selected pair, and bits 07:00 are
N
applied to the ECC vector of the low Qword in the selected
pair.
For Example:
Data Pair Selector bits 17:16 = 00
ECC bit invert vector bits 15:08 are applied to the ECC
vector for QW1
ECC bit invert vector bits 07:00 are applied to the ECC
vector for QW0
Bit Reset
Value
0b
00b
0000h
Bit Access
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
438
August 2009
Order Number: 320066-003US